DCM Doubling

[ShortCircuit]

I am trying to use an external clock source by double it within my design by using a DCM generated within the Xilinx Clocking Wizard. I want to use a 160MHz differential clock, to create a 320MHz single-ended clock. I have created this DCM with internal feedback 1X. I have also used a RST input port, along with a CLK2X & Locked output port.

The wizard creates the following component:
COMPONENT Clock_Double is
PORT (
CLKIN_N_IN : in std_logic;
CLKIN_P_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFGDS_OUT : out std_logic;
CLK0_OUT : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED_OUT : out std_logic);
END COMPONENT Clock_Double;

All of these ports were expected except "CLKIN_IBUFGDS_OUT" & "CLK0_OUT". I do not need these ports and so have left them open as seen below:

ref320Clk: Clock_Double
PORT MAP(
CLKIN_N_IN => ADC0_DRn,
CLKIN_P_IN => ADC0_DR,
RST_IN => s_GSReset,
CLKIN_IBUFGDS_OUT => OPEN,
CLK0_OUT => OPEN,
CLK2X_OUT => s_Clk320MHz_Syn,
LOCKED_OUT => s_DCM320_Locked);

However when implementing this design, it does not pass the MAP process due to the following puzzling error:

ERROR: PhysDesignRules:1710 - Incomplete connectivity. The pin <CLKIN> of comp block <ref320Clk/DCM_ADV_INST> is used and partially connected to network <CLKIN_IBUFGDS_OUT>. All networks must have complete connectivity to the comp hierarchy and the connectivity for this pin must be removed or completed.
ERROR: Pack:1642 - Errors in physical DRC.

I am confused, why does it add in these extra ports? I have tried also connecting them to signals however this did not resolve the error (probably being optimized out). There is effectively no documentation regarding this "CLKIN_IBUFGDS_OUT" port. It shouldn't be this hard to generate a 2X DCM. Can someone please help me resolve this issue?