S
Serkan
Dear Veterans,
I have a design for FPGA whose top module includes 15 vhdl modules
a flexible user/client block that interacts with these blocks . I do
not have the source code for the user block. I just have the inputs
and outputs of this block. I instantiated user block as a black box in
my design. We want to integrate user block into my design without
interchanging the source code from both sides. However, the issue is
that "the synthesis should be done in client's side" and I have the
top module. It should be in a way that once I send the files I am
done. To the client, I want to supply the synthesized version of the
code which client will work for 6 months or so on their user block.
During this time, I will not bother generation of a programming file
for them. I want to make sure they have all the necessary files in
this period.
questions
1- Is there a way other than sending my top module and other 15 edifs
to the client.
2- Is it possible for me to insert client's block as a black box, make
a synthesis and send this file with the ucf file to the client and
make sure that client can integrate his user block and can work
further and generate a programming file.
3- Do I have to make a new top module that has two blocks. One of
this block is my previous top module the other is the user block? I
will put all inputs and outputs of user block to my previous top
module's inputs and outputs in a way that that user block
functionality stays the same.
I prefer 2,3,1. I hope option 2 is aplicable.
I am using Xilinx 9.1.03i, XST,VHDL
I have a design for FPGA whose top module includes 15 vhdl modules
a flexible user/client block that interacts with these blocks . I do
not have the source code for the user block. I just have the inputs
and outputs of this block. I instantiated user block as a black box in
my design. We want to integrate user block into my design without
interchanging the source code from both sides. However, the issue is
that "the synthesis should be done in client's side" and I have the
top module. It should be in a way that once I send the files I am
done. To the client, I want to supply the synthesized version of the
code which client will work for 6 months or so on their user block.
During this time, I will not bother generation of a programming file
for them. I want to make sure they have all the necessary files in
this period.
questions
1- Is there a way other than sending my top module and other 15 edifs
to the client.
2- Is it possible for me to insert client's block as a black box, make
a synthesis and send this file with the ucf file to the client and
make sure that client can integrate his user block and can work
further and generate a programming file.
3- Do I have to make a new top module that has two blocks. One of
this block is my previous top module the other is the user block? I
will put all inputs and outputs of user block to my previous top
module's inputs and outputs in a way that that user block
functionality stays the same.
I prefer 2,3,1. I hope option 2 is aplicable.
I am using Xilinx 9.1.03i, XST,VHDL