How to instantiate a verilog block inside a VHDL entity?

Discussion in 'VHDL' started by thunder, Feb 17, 2014.

  1. thunder

    thunder Guest

    Hello


    My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block.

    QS: Is it possible to instantiate a verilog block inside a VHDL block?
    QS: If the answer to the above question is yes, how to achieve this?

    Thanks in advance

    JO
     
    thunder, Feb 17, 2014
    #1
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  2. Declare a component for the Verilog module and instantiate it just like any
    other VHDL component.

    Check your simulator user's manual for details.
     
    Paul Uiterlinden, Feb 17, 2014
    #2
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  3. thunder

    GaborSzakacs Guest

    The last time I did this with Xilinx tools (ISE) I found I needed to use
    a component instantiation. However I didn't need to do much typing
    because once you add the verilog module to the project you can "View
    instantiation template" which generates the required component
    declaration as well as the instantiation template to paste into your
    VHDL code.

    Some other things to avoid are Verilog port names with upper and lower
    case, especially not having ports that differ *only* in the case of
    the name like:

    module foobar
    (
    input wire FOO,
    input wire Foo,
    output reg foo
    );

    which is legal Verilog, but can wreak havoc when you try to instantiate
    it from VHDL.
     
    GaborSzakacs, Feb 17, 2014
    #3
  4. thunder

    GaborSzakacs Guest

    I've seen other weird problems in XST with mixed language projects. For
    example I found that if I had code in Verilog and VHDL that each used
    the same library primitive (e.g. RAMB16_S9_S9) XST would rename one of
    them with a suffix (e.g. RAMB16_S9_S9_1) and then barf because it
    couldn't find the renamed unit in any library. In general I've found
    mixed language projects to be a headache.
     
    GaborSzakacs, Feb 18, 2014
    #4
  5. thunder

    Daniel Kho Guest

    I suggest for those who like to see this feature supported by Quartus, file a mySupport case with Altera (if you have enough privileges), or submit a post in Altera Forums.

    Based on my experience with Altera, they have the habit of prioritising work based on number of requests filed on a particular topic. If there are many requests regarding a single issue, that issue will receive more attention.

    -daniel
     
    Daniel Kho, Feb 24, 2014
    #5
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