Vhdl instantiating verilog with parameter

Discussion in 'VHDL' started by rizaldo1, Jul 3, 2008.

  1. rizaldo1

    rizaldo1

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    Hello,

    I have a vhdl Top design that instantiates a verilog sub-design.
    This verilog sub-design has a parameter.

    How can I set this parameter in my vhdl top design (when instantiating the verilog design)?

    I know it is possible to do it if the Top design was also written in verilog.
    Is it possible in vhdl?
    Thanks,
    BR,
    Rizaldo1
     
    rizaldo1, Jul 3, 2008
    #1
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