Vhdl instantiating verilog with parameter

[rizaldo1]

Hello,

I have a vhdl Top design that instantiates a verilog sub-design.
This verilog sub-design has a parameter.

How can I set this parameter in my vhdl top design (when instantiating the verilog design)?

I know it is possible to do it if the Top design was also written in verilog.
Is it possible in vhdl?
Thanks,
BR,
Rizaldo1