problem mixing vhdl and verilog using tristate

Discussion in 'VHDL' started by teroer, Jul 26, 2013.

  1. teroer

    teroer

    Joined:
    Jul 26, 2013
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    i have a testbench in vhdl
    and 2 components instancied (one in verilog, one in vhdl) who talks together via a tri state signal cmd .
    when i test it on modelsim i can that the vhd component modifies the cmd signal but not the verilog.
    when i see the same signal in verilog, i see the modification of both. (vhd and verilog)

    i really can't understand why.
    any sugestions?


    tb :
    library ieee;
    use ieee.numeric_std.all;
    use ieee.std_logic_1164.all;
    use IEEE.STD_LOGIC_ARITH.ALL;
    entity otherCom_tb is

    end entity;
    architecture behav of otherCom_tb is
    signal other_cmd,oe1,oe2 : std_logic;
    component othercom is
    port
    (
    oe : in std_logic;
    cmd : inout std_logic
    );
    end component;

    component othercom_vhd is
    port
    (
    oe : in std_logic;
    cmd : inout std_logic
    );
    end component;

    begin
    otherCOM_i1 : otherCOM
    port map
    (
    cmd=>other_cmd,
    oe=>oe1
    );

    otherCOM_i2 : otherCOM_vhd
    port map
    (
    cmd=>other_cmd,
    oe=>oe2
    );

    process
    begin
    other_cmd<='Z';
    oe1<='0';
    oe2<='0';
    wait for 100 us;
    oe1<='1';
    wait for 100 us;
    oe1<='0';
    wait for 100 us;
    oe2<='1';
    wait for 100 us;
    oe2<='0';
    wait;
    end process;
    end architecture;


    othercom_vhd component :
    ----------------------------------------

    library ieee;
    use ieee.numeric_std.all;
    use ieee.std_logic_1164.all;
    use IEEE.STD_LOGIC_ARITH.ALL;
    entity otherCom_vhd is
    port(
    oe : in std_logic;
    cmd : inout std_logic
    );
    end entity;
    architecture behav of otherCom_vhd is
    begin
    cmd <='0' when oe='1' else 'Z';
    end architecture;



    verilog component
    ----------------------------
    `timescale 1ns / 1ps
    ///////////////////////////////////////////////////
    module otherCom(
    input oe,
    tri cmd
    );
    assign cmd = oe ? 1'b0 : 1'bz;
    endmodule
     
    teroer, Jul 26, 2013
    #1
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  2. teroer

    teroer

    Joined:
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    no hints?:stupido3:
     
    teroer, Aug 2, 2013
    #2
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