Hi All,
I want to write an entity/architecture in VHDL and write a testbench in Verilog. I cannot seem to find ANY examples on how to do this. Take the basic up/down counter below for the VHDL portion. How would I interface to this?
I'm using Modelsim. Can I simply create a project, dump the .VHD and .V files into a project and somehow tie them together? I would appreciate seeing the exact Verilog code to do this. Thanks.
I want to write an entity/architecture in VHDL and write a testbench in Verilog. I cannot seem to find ANY examples on how to do this. Take the basic up/down counter below for the VHDL portion. How would I interface to this?
I'm using Modelsim. Can I simply create a project, dump the .VHD and .V files into a project and somehow tie them together? I would appreciate seeing the exact Verilog code to do this. Thanks.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
entity count_up_down is
port (
reset_l : in std_logic;
clk : in std_logic;
preset_l : in std_logic;
load_en : in std_logic;
count_up : in std_logic;
data_in : in unsigned(3 downto 0);
count_out : out unsigned(3 downto 0)
);
end count_up_down;
architecture behave of count_up_down is
signal count_out_i : unsigned(3 downto 0);
begin
-- purpose: count up/down, also has preset and reset
counter: process (clk, reset_l)
begin -- process counter
if reset_l = '0' then -- asynchronous reset (active low)
count_out_i <= (others => '0');
elsif preset_l = '0' then
count_out_i <= (others => '1'); -- preset to 1
elsif clk'event and clk = '1' then -- rising clock edge
if load_en = '1' then
count_out_i <= data_in;
elsif (count_up = '1') then -- count up
count_out_i <= count_out_i + 1;
else -- count down
count_out_i <= count_out_i - 1;
end if;
end if;
end process counter;
-- concurrent signal assignment
count_out <= count_out_i;
end behave;