Configuration for VHDL entity instantiated under Verilog module

Discussion in 'VHDL' started by AnandA, Apr 1, 2009.

  1. AnandA

    AnandA Guest

    I have following hierarchy:

    TB(VHDL) - DUT(VHDL) - Block(Verilog) - Sub-block(VHDL).

    the sub-block(vhdl) has a dummy architecture that I want to use. How
    can I write my VHDL configuration from the TB in order to use the
    dummy architecture of the sub-block?

    AnandA, Apr 1, 2009
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