Configuration for VHDL entity instantiated under Verilog module

[AnandA]

I have following hierarchy:

TB(VHDL) - DUT(VHDL) - Block(Verilog) - Sub-block(VHDL).

the sub-block(vhdl) has a dummy architecture that I want to use. How
can I write my VHDL configuration from the TB in order to use the
dummy architecture of the sub-block?

Thanks,
Anand.