LFSR

[mn19]

Hi,

I'm searching for a VHDL implementation of a LFSR modulo 2 divisor to
calculate the remainder of a polynomial division, with one bit per
clock serial input and the remainder in output.

Can someone send me an example of the VHDL code?

Thank you.

 

[Mike Treseler]

I'm searching for a VHDL implementation of a LFSR modulo 2 divisor

http://groups.google.com/groups/search?q=vhdl+fcs