Hello,\n\nI have a perfect working VHDL code that fills in a RAM\nwith sine sine and cosine tables.\nAll works just fine.\n\nAs soon as I wanted to generate 16K or 32K of tables, bang!\ncompilation aborts and Quartus says it exists loops after 10000 iterations.\nThe help at altera site says it is intentional to prevent (dumb) users\nfrom infinite loops Furthermor they say if one wants more than 10000\niteration go break the loop into more loops below 10000 iterations !!!\n\nHow bizarre !!! couldn't it just issue a warning ?...\n(even DOS asked "are you sure" on del *.*... how funny it would be to\nsee "you are deleting too much files, go delete one by one") Ahhgggg !!!\n\n\nAnyone one knows a way to bypass this ?\nI would hate to slice my beautiful loops. specially as the component\nhas its size passed up on generics.\n\nLuis C.