Measure simulation time in VHDL.

H

harisrini

Hello All,
I was wondering whether there is a way to measure the simulation time
of an event in VHDL.

I am using modelsim simulator with the VHDL capabilites.

To put the same question other way, is there a $time equivalent of
verilog calls in VHDL?

Any answers would be greatly appreciated.

Regards
Hariharan K Srinivasan.
 
B

Ben Jones

Hello All,
I was wondering whether there is a way to measure the simulation time
of an event in VHDL.

I am using modelsim simulator with the VHDL capabilites.

To put the same question other way, is there a $time equivalent of
verilog calls in VHDL?

The built-in VHDL function "now" (which takes no parameters) returns the
current simulation time. Is that what you're looking for?

Cheers,

-Ben-
 
S

sathya

The built-in VHDL function "now" (which takes no parameters) returns the
current simulation time. Is that what you're looking for?

Cheers,

-Ben-

hello all.. please excuse me for my silly doubt..
im really new to VHDL. How do u find help for VHDL online...
Could anyone please tell me how to solve this problem ?
 

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