NOTE: If you are not using 'vmk' utility and are not interested in using\nit you can safely discard this article.\n\nHi everyone,\n\non the wave of a previous article posted here\n(<I am continuing my quest to\nput together a Makefile to handle my vhdl projects.\n\nThanks to 'vmk' I managed to generate a fairly neat Makefile which now\nis happily compiling my set of files in the proper order.\n\nThe 'vmk' utility supports several toolsets to perform compilation and\nsimulation (it also supports an 'elaboration' phase...) but when I\ngenerated the Makefile specific for my toolset (ModelSim), it didn't\nseem to include any target for the simulation.\n\nIn the generated Makefile there are three 'hooks' which are primarily\nmeant to do the following:\n\n1. add a default target or macros\n2. redefine macros or add targets\n3. add additional rules\n\nand I could potentially use 1 or 2 to add a simulation target with all\nthe necessary steps. But I was wondering why the heck 'vmk' has a\ndefined macro for a simulation target and it doesn't use it. Maybe I'm\nmissing something.\n\nSince I would like to use my Makefile for synthesis and place&route as\nwell, I'm looking at using the 2nd hook to add those additional steps.\nIt seems to me there's no way you can define a toolset with a complete\nworkflow (compile, simulate, synthesize, place&route) and you need to\nrely on external hooks to do so.\n\nAny pointer is appreciated.\n\nAl\n\n They are indeed /include/ files passed via an external configuration\nfile.