vmk and simulation


A

alb

NOTE: If you are not using 'vmk' utility and are not interested in using
it you can safely discard this article.

Hi everyone,

on the wave of a previous article posted here
(<I am continuing my quest to
put together a Makefile to handle my vhdl projects.

Thanks to 'vmk' I managed to generate a fairly neat Makefile which now
is happily compiling my set of files in the proper order.

The 'vmk' utility supports several toolsets to perform compilation and
simulation (it also supports an 'elaboration' phase...) but when I
generated the Makefile specific for my toolset (ModelSim), it didn't
seem to include any target for the simulation.

In the generated Makefile there are three 'hooks'[1] which are primarily
meant to do the following:

1. add a default target or macros
2. redefine macros or add targets
3. add additional rules

and I could potentially use 1 or 2 to add a simulation target with all
the necessary steps. But I was wondering why the heck 'vmk' has a
defined macro for a simulation target and it doesn't use it. Maybe I'm
missing something.

Since I would like to use my Makefile for synthesis and place&route as
well, I'm looking at using the 2nd hook to add those additional steps.
It seems to me there's no way you can define a toolset with a complete
workflow (compile, simulate, synthesize, place&route) and you need to
rely on external hooks to do so.

Any pointer is appreciated.

Al

[1] They are indeed /include/ files passed via an external configuration
file.
 
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B

Bart Fox

I use vmk too, but only for simulation.
Since I would like to use my Makefile for synthesis and place&route as
well, I'm looking at using the 2nd hook to add those additional steps.
It seems to me there's no way you can define a toolset with a complete
workflow (compile, simulate, synthesize, place&route) and you need to

I use a second makefile for synthesis and all the stuff.
Here you can find a nice starting point:

https://xess.com/appnotes/makefile.php

Bart
 
A

alb

Hi Bart,

On 09/08/2013 07:11, Bart Fox wrote:
[]
I use a second makefile for synthesis and all the stuff.
Here you can find a nice starting point:

https://xess.com/appnotes/makefile.php

Believe it or not I already had this page open since quite few days,
waiting the right moment to carefully go through, even though I was
trying to understand how vmk works.

Regarding the page you referred to, I have a couple of comments:

1. in your commented section of makefile.mk I guess svf and bit targets
are swapped.

2. When you talk about project makefile you mention about overriding a
PART variable by doing:

<code>
PART = xc2s100-5-tq144
include xilinx_rules.mk
</code>

where I believe that this cannot be since PART is going to take the
*last* assignment to it, not the first. Still you could do overriding
via command line (see GNU make:
http://www.gnu.org/software/make/manual/html_node/Overriding.html). Same
applies for the constraint file variable few lines below.

A 'similar' Makefile was also pointed out by Theo Markettos in this
message <news:4sA*[email protected]>.
 
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B

Bart Fox

Hello Al,
1. in your commented section of makefile.mk I guess svf and bit targets
are swapped.
It's not my makefile, but a suggestion for you.
And yes you are right, the comments are swapped.
Maybe you can drop a mail to xess.
2. When you talk about project makefile you mention about overriding a
PART variable by doing:

<code>
PART = xc2s100-5-tq144
include xilinx_rules.mk
</code>

where I believe that this cannot be since PART is going to take the
*last* assignment to it, not the first. Still you could do overriding
via command line (see GNU make:
http://www.gnu.org/software/make/manual/html_node/Overriding.html).
There is a '?=' in xilinx_rules.mk
See http://www.gnu.org/software/make/manual/html_node/Setting.html#Setting
for explanation.

Bart
 

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