need help to design a VHDL code from an algorithm


L

lokesh kumar

Hi,

I am new to VHDL. I need to design a VHDL code from an algorithm. Can anyone please help me out with it? I am not getting the idea how to implement it..

I want to implement a 163 bit multiplier. So in this case m= 163, w = 32 and
s= [m/w] = 6 (Because my aim is to design for 63 bit. So for I can take 5, 32 bits and one 3 bit at MSB. Hence the value of S is 6 in total)

Here is the algorithm below:

INPUT: A= (As-1, As-2..., A1, A0) and B= (Bs-1, Bs-2,..., B1, B0)
OUTPUT: Z=A.B=(Z2s_1, Z2s-2,..., Z1, Z0)
(U,V) <- (0, 0)
For i from 0 to s-1 do
For j from 0 to s-1 do
(U,V) <- (U,V) + Aj .Bi-j
end for
Zi <- V
V <- U, U <- 0
end for
for i from s to 2s-2 do
for j from i – s+1 to s-1 do
(U,V) <- (U,V) + Aj . Bi-j
end for
Zi <- V
V <- U, U <- 0
end for
Z2s-1 <- V
return Z = ( Z2s-1, Z2s-2, …, Z1, Z0)
---------------------------------------------------------------------------


Variables used:
m = Key length or length of finite field vector (163,233,283, 409, 571)
w = Digit size (32)
s = Number of Digits = [m/w]
i, j = Indexes

A(t), B(t), Z(t) = A finite field element in polynomial basis representation;
A(t) = (am_1, . . . ,a1,a0), where ai is binary, and similarly for B(t)and Z(t)
C(t) = Result of A(t) x B(t); has length 2m- 1
P(t) = Irreducible polynomial
A = (As_1, . . . , A1, A0) Each Ai is a binary vector of size w and similarly for B and Z
U, V = Binary vectors of size w; (U, V) is the concatenation of the two vectors
T0, . . . , T3 = Temporary binary vectors of size w


Really hope someone will help me out. Many thanks!
 
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