Problem with H,Z and inout signals

Discussion in 'VHDL' started by Giox, Apr 1, 2006.

  1. Giox

    Giox Guest

    Hello everybody,
    I have a little problem with my VHDL code.

    I have a situation like the following one:

    pinout/signal_a <--> block_1/signal_b <--> block_2/signal_c

    where <--> indicate an inout port.

    The code looks something like that:

    signal_a <= local_signal

    And on the module that has signal_b as output I put:
    signal_b => local_signal


    During simulation I obtain that when signal_a is H (the expected
    result), while signal_b and signal_c are Z, while when the signal_a is
    0, signal_b and signal_c are coherent.
    The Z value is put on the signal_c by the block_2 and propagated to
    signal_b, while signal_a is connected to a pullup and forced to the
    value H when it is not 0.
    Reading the VHDL standard I found out that the resolution functions
    imposes that when the same line is drove by H and Z the resulting
    signal is H.
    Is there something I'm missing?
    The signals are of type std_logic/std_logic_vector (signal_a is a
    single wire of a std_logic_vector). Any help will be appreciated.
    Gio.
     
    Giox, Apr 1, 2006
    #1
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  2. Mike Treseler, Apr 2, 2006
    #2
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