On Friday, January 11, 2013 3:36:32 PM UTC-6, Nicolas Matringe wrote:
I've always done like that and never had any problem. How else would you code a tri-state output ? Nicolas
Agreed. Just because an output is tri-stated does not mean it is bidirectional. This is how we create open-collector/open-emitter (also called open-drain/open-source) type outputs.
Most FPGA synthesis tools will perform automatic conversion of internal tri-state buses into multiplexers if the target architecture does not support internal tri-states. This works for unidirectional (many drivers, one receiver) as well as bidirectional (many IO ports that drive and receive). In some design architectures, it is much easier/understandable/maintainable to code the tri-state busses than to manually manage the multiplexing. Just leave plenty of comments (and verify that your synthesis tool handles it properly).
Some FPGA synthesis tools (maybe most/all?) will also perform "tri-state pushing" where a chip level tri-state output that needs to be registered can be "retimed" before the tri-state buffer, and the enable for the tri-state buffer also registered. With this technique, you actually (conditionally) assign the output register to 'Z' in RTL, and the synthesis splits that intotwo registers, one for data and another for the implied tri-state buffer enable after the register. In essence, the synthesis tool is "pushing the tri-state" logic to the other side of the register. Then it can push both of those registers into the IOB (assuming the IOB is structured that way) for better timing.
Some synthesizers will combine tri-state to mux conversion with tri-state pushing to allow tri-state busses to "pass through" multiple registers on their way to (or from) the chip level output (or IO).
Read your synthesis manual to find out what it supports.
Andy