Library ieee;
Library work;
use ieee.std_logic_1164.all;
use work.arrays.all;
entity rbf2410 is
port(i : in integer range 0 to 8;
clk : in std_logic;
output : out integer range 0 to ;
end rbf2410;
architecture rbf1 of rbf2410 is
-- signal arr : a1;
begin
process(clk)
variable i : integer range 0 to 8;
variable arr : a1;
begin
if rising_edge(clk) then
i:=i+1;
if (i<7) then
arr(i):=i;
output<=arr(i);
-- i<=i+1;
else
arr(i):=i;
output<=arr(i);
i:=0;
end if;
end if;
end process;
end rbf1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rbf is
generic (
B : natural :=8; -- number of bit
W: natural :=4 -- number of address bit
);
port ( clk, reset : in std_logic;
rd, wr : in std_logic;
w_data : in std_logic_vector ( B-1 downto 0);
empty, full : inout std_logic;
r_data : out std_logic_vector (B-1 downto 0));
end rbf;
architecture Behavioral of rbf is
type array_type is array (0 to 2**W-1) of std_logic_vector( B-1 downto 0);
signal ringbuffer: array_type;
signal w_index, r_index: std_logic_vector( W-1 downto 0); --integer range 0 to 2**W-1;
signal count: std_logic_vector( W downto 0);
begin
empty <= '1' when count=0 else '0';
full <= '1' when count=2**W else '0';
r_data <= ringbuffer( conv_integer(r_index));
process( clk)
variable wr_edge, rd_edge: std_logic_vector( 1 downto 0) := "00";
begin
if rising_edge( clk) then
if reset = '1' then
w_index <= (others=>'0');
r_index <= (others=>'0');
count <= (others=>'0');
wr_edge := wr≀
rd_edge := rd&rd;
else
if wr_edge="01" and full='0' then
ringbuffer( conv_integer(w_index)) <= w_data;
w_index <= w_index+1;
count <= count+1;
end if;
if rd_edge="01" and empty='0' then
r_index <= r_index+1;
count <= count-1;
end if;
wr_edge := wr_edge(0) & wr;
rd_edge := rd_edge(0) & rd;
end if;
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TB_rbf IS
END TB_rbf;
ARCHITECTURE behavior OF TB_rbf IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rbf
PORT( clk : IN std_logic;
reset : IN std_logic;
rd : IN std_logic;
wr : IN std_logic;
w_data : IN std_logic_vector(7 downto 0);
empty : INOUT std_logic;
full : INOUT std_logic;
r_data : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal rd : std_logic := '1';
signal wr : std_logic := '1';
signal w_data : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal empty : std_logic;
signal full : std_logic;
--Outputs
signal r_data : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
--Instantiate the Unit Under Test (UUT)
uut: rbf PORT MAP (
clk => clk,
reset => reset,
rd => rd,
wr => wr,
w_data => w_data,
empty => empty,
full => full,
r_data => r_data);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period*2;
reset <= '0';
w_data <= "00010000";
wait for clk_period*2;
for i in 0 to 17 loop
w_data <= w_data+1;
wr <= '0';
wait for clk_period*2;
wr <= '1';
wait for clk_period*2;
end loop;
for i in 0 to 17 loop
rd <= '0';
wait for clk_period*2;
rd <= '1';
wait for clk_period*2;
end loop;
wait;
end process;
END;
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