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#### Sheetal

VHDL and FPGA implementation..For my project, I'm trying a make a sine

wave, ramp, triangular and square wave generator which outputs

required wave of required amplitude and required frequency

The FPGA is connected with DAC thru I2C bus..

The development board (nanoboard) has on- board freq of 20 mhz...now the

dac being connected to the I2c bus can work upto max 400 Mhz..so a

suitable clock

divisor has to be implemented ..thus a low frequency can be used as

SCL input to DAC..

a)Now, for the sine and square wave, I'm assuming that we can use the

same look-up table(values ranging from 0 to 256)for the output values

of DAC.for obtaining different frequencies, only the SCL needs to be

changed . i.e.if SCl rate is high, the DAC would output from 0 to 256,

then to 0 at a faster rate, if SCL is low, it would output the same

values, but with some delay. THus, variable frequency can be obtained

by changing SCL rate..am I correct in assuming so?

b)If this is correct, can anyone please tell me the relationship

between SCL and output wave frequency..if such a formula/well defined

relationship does exist

c) Also, can anyone tell me about a good link for a simple tutorial on

implementing look-up table?I did find some on the web, but they all

seemed to be complicated..either because they ARE..or because my mind

has gone all-blank right now, with the submission date coming so

near..

Any help at this time would be hugely appreciated

Kind Regards,

Sheetal