Simulating a bidirectional bus delay

Discussion in 'VHDL' started by Fredxx, Jul 15, 2013.

  1. Fredxx

    Fredxx Guest

    I've come to realise that VHDL is not sympathetic to bidirectional bus

    I'm not au fait with Verilog though understand simulating this delay is
    less fraught in Verilog.

    I thought I would use Bidi_Dly.vhd that can be found at:

    However it creates a Hi-Z region around the point of switching that
    causes annoying errors in a Micron DDR2 model.

    I've tried other means but they all seem to fall down when any signal
    goes to 'X'!!

    Can anyone help?
    Fredxx, Jul 15, 2013
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  2. Fredxx

    KJ Guest

    Just curious, how are things any better in Verilog?
    Are you only using the bi-directional model on the true bi-directional signals
    and not, for example, clock? What exactly is the 'annoying error' that the
    Micron model is generating? Are you sure it's not a valid error message (like
    data changing during a write).

    You need to supply more information in order to get some help...

    1. What 'other means' have you tried and in what way did they 'fall down'?
    2. Did the Bidi_Dly.vhd model 'fall down'? If so, in what way?

    3. I haven't used Bidi_Dly.vhd myself, I have my own home grown (not really at liberty
    to share) and didn't have any particular problems when using it with a Micron memory

    4. Exactly what are you trying to model with Bidi_Dly.vhd and why?

    Kevin Jennings
    KJ, Jul 15, 2013
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  3. Fredxx

    Fredxx Guest

    I have only used Bidi_Dly.vhd on bidirectional signals.

    Another model I used was based on:
    process (a)
    if (not(b = a) then
    b <= a after delay;
    end if;
    end process;

    process (b)
    if (not(a = b) then
    a <= b after delay;
    end if;
    end process;

    The issue as soon as one signal goes to X for any reason both become
    stuck at X.

    I'm tying to reconcile differences between a Post-Place and Route
    simulation model and real life, and hoping they might converge if add
    the small PCB and IO delays to the models.

    The DDR2 model I use is:

    * File Name: ddr2.v
    * Version: 5.83
    * Model: BUS Functional
    * Dependencies: ddr2_parameters.vh
    * Description: Micron SDRAM DDR2 (Double Data Rate 2)

    It produces warnings:
    "Invalid latching edge on DQS_N bit"
    from having the DQS lines being tr-stated for 1.0ps during a transition,
    introduced by the Bidi_Dly.vhd.

    Many thanks for your insight.
    Fredxx, Jul 16, 2013
  4. Fredxx

    KJ Guest

    Here is a link to Ben Cohen's Zero ohm resistor model. I've used this model although it too will introduce glitches when the driver changs that might be similar to what you're seeing.,d.aWc

    And here is a link to an alternative model written by someone who tried and did not like Ben's model. I haven't tried it

    Kevin Jennings
    KJ, Jul 17, 2013
  5. Fredxx

    Fredxx Guest

    This model doesn't seem to have a delay associated, apart from a delta
    time so seems I'm missing something here. Like the model I use, there
    is this "Z" during a transition.
    This version doesn't cause the annoying "Z" during a transition, and has
    a generic to add the delay. It seems rather neat in discovering which
    port has control over the other.

    It also means I can undo the modifications to the Micron model!

    Many thanks for your ideas and links.
    Fredxx, Jul 19, 2013
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