The HDL Complexity Tool beta testing.

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The HCT is an open source tool provided free of charge to allow engineers to produce design complexity metrics from HDLs.

We just added VHDL support to our list of parsers and would like beta testers to try it out. I'm the founder of the tool and will check this thread frequently for any feature requests, bugs or questions.

Could you please give it a try on your Windows, Linux or Mac and let us know if you encounter any problems parsing your design? We can use your help!

Find out more on our site. Just point your browser at:
:captain: hct.sourceforge.net

The goal of the HCT is to generate scores that represent the complexity of the constituent modules of large IC design projects – i.e. SOCs. The design's complexity scores are useful to verification teams so as to efficiently focus resources based on the dynamic complexity profile of a design. The scores are a useful tool to guide HDL designer's refactoring efforts. This data provides an efficient way to "come up to speed", by pointing you to the most important modules of a legacy design. Importantly, the complexity scores allow managers to estimate schedules and resources in a more robust and effective way than any one standard metric can provide (SLOC for example).

The metrics that compose the score are derived directly from the HDL source code using a parser. Metrics that are used are chosen to provide a good cross section of complexity. For example, a measure of the Cyclomatic complexity of a module along with the hierarchy of modules within a module are taken into account to produce the score. Metrics are based on well established and published methods. After computing the metrics of a design, they are scaled and then used to create a score by incorporating the user defined weights (yes, there is a default). In this way, a set of scores are "tunable" and therefore provide the greatest amount of flexibility to the user and at the same time are based on standard measurements of the design.
 

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