timing verification

Discussion in 'VHDL' started by alb, Oct 14, 2013.

  1. alb

    rickman Guest

    Can you explain? I'm not following how an assertion will help.

    Counting clock cycles is not the same as timing analysis. That would be
    design verification. I can't think of an example of needing to verify
    something like this. I guess my designs aren't so complex... or maybe
    not so simple?
     
    rickman, Oct 28, 2013
    #21
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  2. alb

    HT-Lab Guest

    Hi Rickman,
    You put an assertion on the control signals of the path so that the
    assertion will fire/fail when the false path is selected (i.e. data
    flows through the path). Tools like Fishtail generates the false path
    assertions automatically for you.

    ...
    true, using assertions for false and multi-cycle path is merging
    functional and timing verification. However, your static timing tool is
    not going to tell you if you path is false or not, it just give you the
    propagation delay.

    Regards,
    Hans.
    www.ht-lab.com
     
    HT-Lab, Oct 29, 2013
    #22
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  3. 'n clocks' type verifications for a synchronous design that meets
    I just use a fast enough clock so that these are all synchronous and
    covered by the testbench.
    Even in this case, the clock constraint must match the hardware.
    Duty cycle etc.
    No. It's a mess. Trial and error.
    Synopsis/Quartus sdc works the best.
    https://www.google.com/search?q=sdc+file+example

    Good luck
    -- Mike Treseler
     
    Mike Treseler, Oct 29, 2013
    #23
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