[QUOTE]\nHi Rickman,\n\nOn 15/10/2013 23:42, rickman wrote:\n...\n\nYou use assertions to make sure that your timing constraints itself are\ncorrect. For example, there are occasions where it is not easy to\ndetermine if you always have a multi-cycle path (e.g. a designs with\nmultiple clock domains). In this case an assertion can help (or prove\nexhaustively if you use a formal tool). For false path an assertion even\nbecomes a must have as checking them manually (i.e. looking at a gate\nlevel schematic!) is an error prone and a very time consuming activity.[/QUOTE]\n\nCan you explain? I'm not following how an assertion will help.\n\n[QUOTE]\nYou can quite easily add an embedded assertion (supplied with the design\nitself) that always checks that A happens 3 clock cycles after B. The\nproblem with Verilog/VHDL is that they are very verbose and hence more\nsusceptible to bugs, languages like PSL/SVA are designed for this task\nand hence are very concise, easy to use for sequences and un-ambiguous.\nYou can write a page of VHDL/Verilog or 1 line of PSL/SVA.[/QUOTE]\n\nCounting clock cycles is not the same as timing analysis. That would be\ndesign verification. I can't think of an example of needing to verify\nsomething like this. I guess my designs aren't so complex... or maybe\nnot so simple?