Verilog RTL and Behavioral Testbench

Discussion in 'VHDL' started by Davy, Mar 25, 2006.

  1. Davy

    Davy Guest

    Hi all,

    I am reading the book "Writing Testbench" and found my previous
    testbench style is RTL.
    Can I change Verilog RTL Testbench to Behavioral Testbench, is the
    below code right?

    //---- RTL style---
    [email protected](posedge clk)

    //----Behavioral style---
    Always begin
    @(posedge clk);

    Is there any other better Behavioral style?

    Any suggestions will be appreciated!
    Best regards,
    Davy, Mar 25, 2006
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  2. Davy

    sharp Guest

    This "Behavioral style" is an attempt to optimize for faster
    simulation. In reality, it may end up running a lot slower, depending
    on your simulator.
    sharp, Mar 26, 2006
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