V
vipin lal
VHDL tutorial site for beginners..many vhdl tips are explained in a
simpler way.
http://vhdlguru.blogspot.com/
simpler way.
http://vhdlguru.blogspot.com/
VHDL tutorial site for beginners..many vhdl tips are explained in a
simpler way.http://vhdlguru.blogspot.com/
VHDL tutorial site for beginners..many vhdl tips are explained in a
simpler way.http://vhdlguru.blogspot.com/
A "guru" wouldn't use the deprecated std_logic_arith, and a guru
wouldn't use "if (clk'event and clk='1')" when "if rising_edge(clk)"
is available.
And a guru would figure out how to show code using a proper font.
-a
A "guru" wouldn't use the deprecated std_logic_arith, and a guru
wouldn't use "if (clk'event and clk='1')" when "if rising_edge(clk)"
is available.
And a guru would figure out how to show code using a proper font.
I will try to avoid the use of SLV as much as possible..
I'm not sure that's the lesson to take from Andy's explanation. If I
may be allowed to interpret here, you should use the data type that
fits the data you are representing by that symbol. If you are
shipping around numbers, use unsigned or signed as appropriate. If
you are shipping around discrete logic, use std_logic and
std_logic_vector. The general thrust is that the language supports a
wide variety of data types and to the extent made possible by the EDA
tools, we should use those language features in an intelligent manner
to accurately represent the design we are building.
vipin said:I will try to avoid the use of SLV as much as possible..
Yes, M Norton has correctly interpreted what I wrote:
Generally, if you can, create your entity interfaces using unsigned
or
signed (or even integer)
!!!if they are uniformly numerically interpretted.!!!
(i.e. a generic memory device may be able to store any
kind of binary data, so SLV may make more sense there, but a digital
filter has a specific definition of its input data in mind, and that
can be coded by using the appropriate type on the port. Using the
appropriate types on the ports makes it much easier to avoid
conversions within the body.
There are many places where unsigned or signed should rightly be used
instead of SLV, but there are also many places where a single numeric
interpretation of the data is not supported, and the more general SLV
remains appropriate.
For example, an ALU that accepts signed or unsigned data (depending on
the operation control) may always have a numeric interpretation of the
data on its ports, but since we do not have a generic numeric signed
and unsigned representation, SLV would still be appropriate for those
ports.
Other examples, as Norton pointed out, include any collection of bits
that does not have a numeric meaning such as a vector of enable bits,
etc.
Andy
Hi...
Yeah..I misunderstood Andy in the beginning.Now I got it.
One more doubt.
IS there any math library in VHDL for operations such as square
root,floating point operations etc.Or you should make them your own
according to your own needs?
I am trying to write some functions of some basic operations.But if
any reliable standard library is there,then I can use them instead.
Thanks
vipin
The fixed point packages can be used, by specifying zero fractional
(negative indexed) bits, to represent signed and unsigned integer
arithmetic. The fixed point packages assume a more integer-like tilt
toward numeric accuracy than numeric_std does, by expanding the sizes
of results to accurately handle the possible nnumeric range of those
results. So adding two n bit ufixed operands results in an n+1 bit
result. This means that intermediate results in expressions are
numerically accurate (not subject to truncation, except for division),
but due to the inability to override assignment operators inVHDL, the
results usually must be manually re-sized to store in a variable or
signal. Just like with integers, synthesis should be able to do a good
job of removing bits and logic associated with expanded intermediate
results if they do not contribute to those bits retained in storage.
So an up counter would look something like:
variable n : ufixed(nsize - 1 downto 0);
...
-- resize does the rollover
n := resize(n + 1, n);
My biggest disappointment with the fixed point package is that
subtraction of two ufixed operators does not expand the result to
sfixed (but it does expand the size of the results by one bit, which
will always be zero!) So while the ufixed + operator does not roll
over, the - operator for ufixed does, however by some perverse stroke
of luck, you still have to manually resize the result:
variable n : ufixed(nsize - 1 downto 0);
...
-- ufixed subtract does the rollover,
-- resize is still required
n := resize(n - 1, n);
Comparatively, with integers:
variable n : integer range 0 to 2**nsize - 1;
...
-- integer mod does the rollover
n := (n - 1) mod 2**nsize;
And with unsigned:
variable n : unsigned(nsize - 1 downto 0);
...
-- unsigned subtract does the rollover
n := n - 1;
Andy
I am using Xilinx ISE 10.1Thanks Andy..
I started using fixed_pkg and wrote some simple programs also.But when
I tried to synthesis the code it came "Library ieee_proposed cannot be
found."
I successfully simulated the same design.
Is Library ieee_proposed not synthesisable????????
pls help...
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