VHDL Generics problem when simulating SDF with Scirocco

[Fazela]

Hi All,
We have a simple sequential VHDL counter design. We converted it into
structural VHDL using Design Compiler and also wrote out its SDF file.
Now to perform post synthesis simulation with the SDF file, we are
using Scirocco simulator with following command line:
../scsim -sdf /tb_counter/UUT/:counter.sdf

Since this is a school project we are just using the freely availabe
OSU standard cell library for synthesis and simulation. There are a
couple of errors that we are just not being able to solve:

(SDF File: counter4.sdf Line: 68) generic
/TB_COUNTER/UUT/ADD_21_PLUS_PLUS/U1_1_6/TPD_A_YS_posedge
is not declared
Error: simulation scsimElab vhdl-252
(SDF File: counter4.sdf Line: 69) generic
/TB_COUNTER/UUT/ADD_21_PLUS_PLUS/U1_1_6/TPD_A_YS_negedge
is not declared

I do not understand where these generics need to be declared. The OSU
standard cell VHDL file has these generics, then why are they not being
incorporated in the synthesized design during compilation? Is there
some step that we are missing over here.

Any comments or help would be greatly appreciated.

Thanks a lot,
FV

 

[Ajeetha]

Hi,
Can you send a testcase? From text it doesn't look like any thing is
wrong, need to see the actual code to debug further. Ofcourse the best
option *might* be that you contact (e-mail address removed), but if you
feel like, send the same to ajeetha <> gmail.com. I do NOT promise a
timeline, but I've access to VCSMX and hence *may* be able to look into
it. BTW, what is your VCSMX version?

Regards
Ajeetha, CVC
www.noveldv.com