Components with GENERICs

[Analog_Guy]

I am interested in writing a VHDL testbench for a VHDL component with
several generics. How do I go about changing the generics during the
course of a simulation?

It is my understanding that the generic values are fixed per a given
compile of the code. I can easily manipulate ports during a
simulation, but not generics.

Can this be done through a configuration, whereby I generate a number
of configurations for each set of generic values I wish to simulate?
I would then compile the configurations, and run each separately in
ModelSim. Is there an easier way to do this on the fly with only one
simulation file?

 

[Jonathan Bromley]

I am interested in writing a VHDL testbench for a VHDL component with
several generics.  How do I go about changing the generics during the
course of a simulation?

You can't. Generics are constants, established at elaboration
time. They are fixed for the life of the sim. Not surprising
given that you can use a generic to control things like the
width of a data bus or the number of instances of a component -
it's hard to imagine changing those things at runtime!

Can this be done through a configuration, whereby I generate a number
of configurations for each set of generic values I wish to simulate?

Absolutely. However, the syntax is ugly and Not Memorable,
and many people steer clear of them.

Is there an easier way to do this on the fly with only one
simulation file?

Modelsim (and, I'm pretty sure, other simulators too) allow you
to set generics from the command line that loads the simulation.
This provides a convenient short-cut to avoid writing a
configuration or top-level wrapper. Look up the -g and -G
options to the vsim command. I'm afraid I can't help you
with any of the other simulators, which I tend to use only
for Verilog.

 

[Andy Rushton]

I am interested in writing a VHDL testbench for a VHDL component with
several generics. How do I go about changing the generics during the
course of a simulation?

It is my understanding that the generic values are fixed per a given
compile of the code. I can easily manipulate ports during a
simulation, but not generics.

Can this be done through a configuration, whereby I generate a number
of configurations for each set of generic values I wish to simulate?
I would then compile the configurations, and run each separately in
ModelSim. Is there an easier way to do this on the fly with only one
simulation file?

Yes, remember that VHDL is a concurrent language. So why not create
multiple instances in one test bench, each with different generic
values? You could wrap them in a for-generate too to generate all
permutations of the generic if that suits what you are trying to do.

I do this sometimes to do comparisons between different word-lengths to
see how it affects result accuracy. By simulating different sizes side
by side I can plot the output difference as a waveform in ModelSim.

Andy

 

[Analog_Guy]

Yes, remember that VHDL is a concurrent language. So why not create
multiple instances in one test bench, each with different generic
values? You could wrap them in a for-generate too to generate all
permutations of the generic if that suits what you are trying to do.

I do this sometimes to do comparisons between different word-lengths to
see how it affects result accuracy. By simulating different sizes side
by side I can plot the output difference as a waveform in ModelSim.

Andy

Thanks to both of you for your great suggestions. I never thought of
those
approaches! Thanks again for your help ... much appreciated.