Noob doubt about components

[Ricewind]

Hallo. I am currently starting a project in VHDL and I am trying to learn a bit for getting the first steps...

I have been trying to do a simple component and to compile and simulate it through Xilinx System generator.

In one HDL file i have the following code:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

entity System68 is
port(
A : in Std_Logic;
B : in Std_logic;
Sal : out std_logic
);
end System68;

architecture my_computer of System68 is

signal Senh1 : std_logic;
signal Senh2 : std_logic;
signal Senh3 : std_logic;

component miniand is
port (
Ent1 : in Std_Logic;
Ent2 : in Std_Logic;
Sal1 : out Std_Logic
); --
end component;


begin

my_and : miniand port map (
Senh1 => Ent1,
Senh2 => Ent2,
Senh3 <= Sal1

);

A=>Senh1;
B=>Senh2;
Sal<=Senh3;

end my_computer;



I have the component stored in another HDL file in the same folder as the previous one:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity miniand is
port (
Ent1 : in Std_Logic;
Ent2 : in Std_Logic;
Sal1 : out Std_Logic
);
end entity;

architecture uart of miniand is

begin

Sal1 <= Ent1 AND Ent2;


end uart;


I cannot simulate it propperly, as the SG shows me the following error:

HDL simulation model compilation failed.
ERROR:HDLCompiler:435 - "xlisim_System68.vhd" Line 1805: Formal senh1 is not declared
ERROR:HDLCompiler:432 - "xlisim_System68.vhd" Line 1804: Formal <ent1> has no actual or default value.
ERROR:HDLCompiler:806 - "xlisim_System68.vhd" Line 1811: Syntax error near =>.
ERROR:HDLCompiler:841 - "xlisim_System68.vhd" Line 1811: Expecting type void for <senh1>.
ERROR:HDLCompiler:806 - "xlisim_System68.vhd" Line 1812: Syntax error near =>.
ERROR:HDLCompiler:841 - "xlisim_System68.vhd" Line 1812: Expecting type void for <senh2>.
ERROR:HDLCompiler:854 - "xlisim_System68.vhd" Line 1787: Unit <my_computer> ignored due to previous errors.
ERROR:HDLCompiler:854 - "xlisim_System68.vhd" Line 1823: Unit <xlisim_system68> ignored due to previous errors.
ERROR:HDLCompiler:374 - "xlisim_System68.vhd" Line 1831: Entity <xlisim_system68> is not yet compiled.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1832: <string> is not declared.
ERROR:HDLCompiler:631 - "xlisim_System68.vhd" Line 1833: Near string "compilacion,sysgen_core_11_1_1666,{total_blocks=12,xilinx_black_box_block=1,xilinx_gateway_in_block=2,xilinx_gateway_out_block=1,xilinx_system_generator_block=1,}" ; 0 visible types match here
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1835: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1836: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1837: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1840: <a_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1841: <b_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1842: <sal> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1846: <a_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1847: <b_net> is not declared.

Error occurred during "Simulation Initialization".


Reported by:
'compilacion/Black Box'


I suppose it is a pretty noobish question but i do not get to solve it... even with the manuals and tutorials I have got.

Thank you very much in advance.

 

[nicx82]

Change:
A=>Senh1;
B=>Senh2

To:
Senh1<=A;
Senh2<=B;

 

[Ricewind]

Error again...

HDL simulation model compilation failed.
ERROR:HDLCompiler:435 - "xlisim_System68.vhd" Line 1805: Formal senh1 is not declared
ERROR:HDLCompiler:432 - "xlisim_System68.vhd" Line 1804: Formal <ent1> has no actual or default value.
ERROR:HDLCompiler:854 - "xlisim_System68.vhd" Line 1787: Unit <my_computer> ignored due to previous errors.
ERROR:HDLCompiler:854 - "xlisim_System68.vhd" Line 1823: Unit <xlisim_system68> ignored due to previous errors.
ERROR:HDLCompiler:374 - "xlisim_System68.vhd" Line 1831: Entity <xlisim_system68> is not yet compiled.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1832: <string> is not declared.
ERROR:HDLCompiler:631 - "xlisim_System68.vhd" Line 1833: Near string "compilacion,sysgen_core_11_1_1666,{total_blocks=12,xilinx_black_box_block=1,xilinx_gateway_in_block=2,xilinx_gateway_out_block=1,xilinx_system_generator_block=1,}" ; 0 visible types match here
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1835: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1836: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1837: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1840: <a_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1841: <b_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1842: <sal> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1846: <a_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1847: <b_net> is not declared.
ERROR:HDLCompiler:69 - "xlisim_System68.vhd" Line 1848: <sal_net> is not declared.
ERROR:HDLCompiler:192 - "xlisim_System68.vhd" Line 1848: Actual of formal out port sal cannot be an expression

Error occurred during "Simulation Initialization".


Reported by:
'compilacion/Black Box'



I suppose it must be something related with have both things in different files, or not having compiled something... but supposely System Generator does not need previous compilation. Is the way I am doing the refering between the main program and the component correct?

 

[joris]

The port mapping is done the other way around:

my_and : miniand port map (
Ent1 => Senh1,
Ent2 => Senh2,
Sal1 => Senh3
);

BTW, why do you have:

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

I think you should use either ieee.numeric_std or the IEEE.STD_LOGIC_ARITH/IEEE.STD_LOGIC_UNSIGNED combo, but you should prefer ieee.numeric_std for new designs.
For your code you don't need any of the three at all really!