vhdl left register

[CS_]

can anyone solve this



Write the VHDL Code for a 16-bit shift left register

 

[jeppe]

Hi

Find inspiration in this:

process( clk)
begin
     if rising_edge( Clk) then
        if reset='1' then
             Shreg <= (others=>'0');
        else
             Shreg <= Shreg( 14 downto 0) & Databit;
        end if;
    end if;
end process;