Viewing intermediate variable value within a process in ModelSim

Discussion in 'VHDL' started by rwdfan, Feb 18, 2010.

  1. rwdfan

    rwdfan Guest

    I am debugging a VHDL block which has a "for loop" inside a
    procedure. Within each iteration of the for loop, a variable is
    conditionally assigned. For troubleshooting the design, I am
    interested in viewing the value of the variable at specific locations
    of the process. Since the variable is re-assigned subsequently within
    the process, the variable has changed state multiple times in zero
    time. I realize this rules out any viewing in a wave window.

    process(clk,reset)
    variable a;
    variable b;
    begin
    if rising_edge(clk) then
    for i in 0 to 7 loop
    if condition1 then
    a := x(i);
    end if;
    b := a;
    if condition2 then
    a := x(i+1);
    end if;
    end for;
    end if
    end process;

    Here is a simple example. Please do not recommend a different coding
    style, as this is merely an attempt to illustrate the problem. Let's
    say I want to lok at the value of a (or i, for that matter) at the end
    of the first if statement. I do not want to see it after the process
    completes. I would be happy if I could insert a line of code similar
    to the report command, that could display the value of a variable at
    the time of execution.

    Any suggestions?
    Brett
     
    rwdfan, Feb 18, 2010
    #1
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  2. Not true.
    If I name the process, I can add it by name with an "add wave" command.
    However, only the final value is shown on the wave.
    You can do exactly that in simulation.

    With modelsim, I just say STEP at the command line,
    and watch the variables as the code comes into scope.

    -- Mike Treseler
     
    Mike Treseler, Feb 18, 2010
    #2
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  3. rwdfan

    backhus Guest

    Hi,
    with Modelsim you also have the option to use the LIST view.
    This can be expanded to show each delta cycle, and the changes of a
    value in a loop should cause delta cycles.
    So you should be able to see the behavior of your variable there.

    Have a nice simulation
    Eilert
     
    backhus, Feb 19, 2010
    #3
  4. Really? If that's true, then VHDL is far too much like
    Verilog for my taste :)
     
    Jonathan Bromley, Feb 19, 2010
    #4
  5. rwdfan

    HT-Lab Guest

    Just a side note, the waveform window is much easier for looking at Delta
    cycles, this is supported in 6.5x and later.

    Hans
    www.ht-lab.com
     
    HT-Lab, Feb 19, 2010
    #5
  6. I am debugging a VHDL block which has a "for loop" inside a
    I assume this is a ModelSim issue.

    Just set up a signal to mirror all variables.

    Use two or more signals to take care of your
    zero time issue. Perhaps put a flag signal
    in each of your if statements. You should be
    able to see anything reasonable.

    Brad Smallridge
    AiVision
     
    Brad Smallridge, Feb 22, 2010
    #6
  7. rwdfan

    Andy Guest

    Jonathan eluded to this, but here's another hint:

    Delta cycles occur at suspensions of processes. Thus the iterations of
    a loop in a process (so long as the loop does not contain a wait
    statement) do not generate delta cycles.

    I suppose you could insert "wait for 0 ns;" inside the loop, and it
    would generate delta cycles for each loop iteration.

    Like Mike and others, I use breakpoints, single-stepping, etc., or I
    use a report/assert statement.

    Andy
     
    Andy, Feb 22, 2010
    #7
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