weak pull up and pull down

K

krithiga81

Hello
I have a Verilog model that uses

rtran(P_P, PADP_i);
rtran(P_M, PADM_i);

If I model this in VHDL, P_P and P_M are pulled up and down and I
cannot use signal assignments in VITAL as I am in a process which
complains if I do so. How do I model these in VITAL in VHDL?

Thanks
krithiga
 

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