xilinx boards

[Amit]

hello group,

as part of small project I need to send data from a PC (via RS232) to
xilinx board i.e. virtex. is this possible if so, can somebody give me
some insight and where to start?

thanks,
amit

 

[valentin tihhomirov]

Appreciate the code worked for me. For voltage conversion, look
somewhere else.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232_RECEIVER is
port (
CLK : in std_logic; -- system clock signal
RESET : in std_logic; -- Reset input
ENABLE : in std_logic; -- Enable input
Rx : in std_logic; -- RS-232 data input
ON_BYTE : out std_logic; -- pulses at start or stop bit signaling new byte
SHIFTING: out std_logic -- pulse on input
);
end RS232_RECEIVER;


architecture RTL of RS232_RECEIVER is
begin


OVERSAMPLING_RECEIVER: block
signal BIT_POS, BIT_POS_NEXT: integer range 0 to 9;
signal SAMPLE_CNT, SAMPLE_CNT_NEXT: std_logic_vector(3 downto 0);

begin

COMB : process(Rx, SAMPLE_CNT, BIT_POS)
begin

SHIFTING <= '0';

if SAMPLE_CNT = 0 and BIT_POS = 0 and Rx = '1' then
SAMPLE_CNT_NEXT <= "0000";
else -- start bit
SAMPLE_CNT_NEXT <= SAMPLE_CNT + 1;
end if;


BIT_POS_NEXT <= BIT_POS;
ON_BYTE <= '0';

if SAMPLE_CNT = 7 then -- middle of bit slice
if BIT_POS = 0 then -- start bit
ON_BYTE <= '1';
elsif BIT_POS = 9 then
-- stop bit, cease reception
BIT_POS_NEXT <= 0;
SAMPLE_CNT_NEXT <= "0000";
else -- data bit
SHIFTING <= '1';
end if;
elsif SAMPLE_CNT = 15 then-- move to next bit
BIT_POS_NEXT <= BIT_POS + 1;
end if; -- SampleCnt

end process COMB;

REG: process (RESET, CLK, Rx)
begin
if RESET = '1' then -- Reset
BIT_POS <= 0;
SAMPLE_CNT <= "0000";

elsif Rising_Edge(CLK) then
if ENABLE = '1' then

SAMPLE_CNT <= SAMPLE_CNT_NEXT;
BIT_POS <= BIT_POS_NEXT;

end if; -- ENABLE
end if; -- CLK

end process REG;


end block OVERSAMPLING_RECEIVER;

end RTL;






library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity UART_TRANSMITTER is
port (
CLK : in std_logic; -- system clock signal
RESET : in std_logic; -- Reset input
ENABLE : in std_logic; -- Enable input
RUN : in std_logic; -- '1' enables transfer
SIN : in STD_LOGIC; -- serial input
SHIFTING: out std_logic; -- pulse on bit output, user provides
next data bit on next clock
Tx : out std_logic -- RS-232 output
);
end UART_TRANSMITTER;

architecture RTL of UART_TRANSMITTER is
function TO_STD( V: Boolean ) return std_logic is
begin
if V then
return '1';
else
return '0';
end if;
end TO_STD;
begin

OVERSAMPLING: block
constant BIT_POS_INIT: integer := 9;
signal SAMPLE_CNT, SAMPLE_CNT_NEXT: std_logic_vector(3 downto 0);

signal BIT_POS, BIT_POS_NEXT: integer range 0 to 9 := BIT_POS_INIT;
begin

COMB : process(SAMPLE_CNT, BIT_POS, RUN)
begin

-- defult values
SHIFTING <= '0';
SAMPLE_CNT_NEXT <= SAMPLE_CNT + 1;
BIT_POS_NEXT <= BIT_POS;

if SAMPLE_CNT = 15 then

if BIT_POS = 9 then --stop condition
BIT_POS_NEXT <= 9;
SAMPLE_CNT_NEXT <= "1111";
if RUN = '1' then -- start condition
BIT_POS_NEXT <= 0;
SAMPLE_CNT_NEXT <= "0000";
end if;
else
BIT_POS_NEXT <= BIT_POS + 1;
SHIFTING <= TO_STD(BIT_POS /= 0);
end if;

end if;

end process;

REG: process(CLK, RESET)
begin
if RESET = '1' then -- Reset
BIT_POS <= 9;
SAMPLE_CNT <= "1111";

elsif Rising_Edge(CLK) then
if ENABLE = '1' then
BIT_POS <= BIT_POS_NEXT;
SAMPLE_CNT <= SAMPLE_CNT_NEXT;
end if;
end if;

end process;

with BIT_POS select
Tx <= '0' when 0,
'1' when 9,
SIN when others;

end block OVERSAMPLING;

end RTL;

 

[Andy]

I understand that this is an example, and that the OP will need to
modify it or add to it per their purposes, but...

If you let the user set the period of the sample counter (via a
generic or a port), and you simply use half that sample period as your
sampling point (divide by two is free in HW), then the user can use
this module, untouched, for almost any baud rate and clock frequency,
without having to generate a clock enable timebase, so long as the
counter does not get too big or too small (2 < n < 2**31 - 1, for a
natural counter).

A few coding related recommendations:

Use numeric_std packages which contain SL-based types and operators
for unsigned and signed arithmetic, or bettter yet, use integer
subtypes (which you did for bit_pos, but not sample_cnt). Std_logic_
[arith/signed/unsigned] are _NOT_ IEEE controlled, standard packages,
and their implementations can vary across different tools.

Adopt a single process coding style with the following advantages: it
uses fewer signals, has simpler sensitivity lists, cannot generate
latches, integrates clock enable and functional behavior, is more
efficient to simulate, and allows optimal use of variables. If you
MUST use combinatorial processes (doubtful), put all of your default
assignments right up front in the process. This makes auditing/
reviewing your combinatorial process simpler to ensure that every
output is written in every execution of your process (to avoid
latches). I understand that most textbooks still promote dual
combinatorial & clocked process pairs, but the state of the art in
industry has moved beyond that for the most part.

When possible, avoid combinatorial outputs from architectures in
synthesizable code. This avoids glitches on outputs, and simplifies
timing optimizattion.

I hate to discourage using a block statement (they are often not used
when they should be), but you should avoid using blocks which are
redundant with the architecture's scope. It needlessly extends net
names in the synthesis netlist, not to mention the source code and
indentation levels. Blocks are a useful structure to limit scope
within an architecture that contains multiple processes, or
combinatorial/clocked process pairs (I prefer only clocked processes
with variables, but a block for each pair can accomplish the same
scope control with signals).

Andy