xilinx ise synthesis timing summary

[niyander]

hi,

i have made a floating point multiplier and after synthesis i get the
following result.
does the "No path found" message means that my design is not
synthesized properly?

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 18.621ns

please help me.

thanks

 

[sridar]

Re:

Looks like you didn't use any clock in your design. Since you use only combinational logic, the particular info " Maximum combinational path delay" is displayed.

 

[vipin lal]

hi,

i have made a floating point multiplier and after synthesis i get the
following result.
does the "No path found" message means that my design is not
synthesized properly?

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 18.621ns

please help me.

thanks

No, "no path found" doesnt mean that your code is not synthesised
properly. I found this answer from xilinx forum:

"The PERIOD constraint only applies to internal signals which go from
one flip-flop to another on the same clock."

Your design doesnt use a clock,so no flip flops are generated. So the
maximum operating frequency is not a function of internal timing and
cannot be calculated during synthesis.

Experts please verify this.

--vipin

 

[backhus]

No, "no path found" doesnt mean that your code is not synthesised
properly. I found this answer from xilinx forum:

"The PERIOD constraint only applies to internal signals which go from
one flip-flop to another on the same clock."

Your design doesnt use a clock,so no flip flops are generated.  So the
maximum operating frequency is not a function of internal timing and
cannot be calculated during synthesis.

Experts please verify this.

--vipin

Hi,
vipins interpretation is correct.

It may make one wonder that a FP-multiplier has no FFs at all, but if
it's intended, why not.
18 ns (including the slow I/O-buffers) allow operations up to 55 MHz.

To be sure that everything went well you may check the amount of
primitives (BELs) in the synthesis report, also check all the warnings
and infos.
A post translate/map/par simulation will show you quite fast wether
the synthesized logic works as intended or not. Be prepared to see a
lot of glitches.

Have a nice synthesis
Eilert