Maximum combinational path delay

Discussion in 'VHDL' started by samehsh, Jun 21, 2008.

  1. samehsh

    samehsh

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    I have an combinational circuit will running in ISE Xilinx i get these result does Maximum combinational path delay mean circuit time complixity or i must compute it by another way....



    TIMING REPORT

    NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
    FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
    GENERATED AFTER PLACE-and-ROUTE.


    Clock Information:
    ------------------
    No clock signals found in this design

    Asynchronous Control Signals Information:
    ----------------------------------------
    No asynchronous control signals found in this design

    Timing Summary:
    ---------------
    Speed Grade: -8

    Minimum period: No path found
    Minimum input arrival time before clock: No path found
    Maximum output required time after clock: No path found
    Maximum combinational path delay: 27.429ns
     
    samehsh, Jun 21, 2008
    #1
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