Co simulation of SystemC files with VHDL testbench

Discussion in 'VHDL' started by doromdor, Dec 7, 2009.

  1. doromdor

    doromdor

    Joined:
    Nov 17, 2009
    Messages:
    2
    Sorry if this is not the correct place to post my question,

    I am intrested in co-simulation of VHDL and systemC

    I want to use VHDL testbench in order to test systemC files

    The programs I am using for this are Questasim and Modelsim (of mentor graphics)

    Anyone has a good tutorial about this or can explain me how it is done ?



    Thanks in advance ,

    Dor
    doromdor, Dec 7, 2009
    #1
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