'event is synthesizable. 'last_value is not necessarily
portable in synthesis (if it is supported at all).
For edge detection of a clock for synthesis in user code
with an "if" statement, I recommend using either rising_edge
or if you must roll your own then: clk = '1' and clk'event.
'last_value allows one to be "for-sure for-sure", however,
for clocks this should not be necessary. Clocks are sacred
and if they go to 'X' after they start up, something is very
wrong and if this is a possibility, having one centralized
assertion to kill the simulation would be sufficient and
more efficient than having each register clock edge check and
see if it is a valid edge. For example:
Clk_watcher: process
begin
wait until is_x(Clk) ;
if now > CLK_START_UP_TIME then
report "clock is X" severity failure ;
end if ;
end process ;
Note, I would only do this if there was something in the clock
circuitry that gave it the possibility of going to X.
I'd like to use to test rising/falling edge of a signal.
I think it should be synthesizable because std_logic_1164.rising_edge() uses
this attribute. I assume when I can use std_logic_1164.rising_edge() I can
use "last_value" also
False assumption.
There is lots in the standard packages that is not synthesized,
but instead, simply known. Some of this is accomplished by
using vendor specific attributes.
Im not familiar with synthesis (now), I just want write a package which
items are synthesizable also. I prefer using attributes instead of using
functions from "std_logic_1164".
Start simple. There is no reason to write a package early on.
Learn the basics of synthesizable code first.
Cheers,
Jim