last_value

Discussion in 'VHDL' started by Account1, Dec 22, 2006.

  1. Account1

    Account1 Guest

    Hi,

    The last_value attribute is synthesizable?

    Could you suggest a link about the synthesizable subset of vhdl?

    Thanks
    Attila
    Account1, Dec 22, 2006
    #1
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  2. Hi Account1,

    Account1 schrieb:
    > The last_value attribute is synthesizable?


    What gate would you like the synthesiser to use, in order to synthesis
    signal'lastvalue?
    If you have a good idea, you should discus this issue with tool
    vendors.

    > Could you suggest a link about the synthesizable subset of vhdl?


    ieee 1076.6. Unfortunately you need to be member of ieee to have free
    access to this document.

    bye Thomas
    Thomas Stanka, Dec 22, 2006
    #2
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  3. Account1 wrote:

    > The last_value attribute is synthesizable?


    Don't know. Try it and see, but signal attributes like
    last_value have traditionally been weak points for synthesis.

    I prefer to describe logic using the present value of
    variables and leave the signals for port maps.
    ....
    last_n_v := n_v;
    n_v := n_v + 1;
    ....

    > Could you suggest a link about the synthesizable subset of vhdl?


    My short answer is:
    Do use a synchronous process.
    Don't use "wait for".
    Do start with some known-good examples.

    My long answer is the template examples here:
    http://home.comcast.net/~mike_treseler/

    ieee 1076.6 is an applicable standard,
    but that is more a collection of compliant cases
    than a best practices document for designers.
    I have never seen an IP core claiming ieee 1076.6 compliance.
    I'm not sure how that could be proven and if
    it were, the IP might still have other problems.


    -- Mike Treseler
    Mike Treseler, Dec 22, 2006
    #3
  4. Account1

    Jason Agron Guest

    Unfortunately, there is no standard synthesizable subset of VHDL
    (especially for attributes which are essentially compiler directires),
    however individual synthesis tools will have such standards. For
    instance Xilinx defines the subset for XST in a file called the "XST
    User's Guide" that can be found here...

    http://toolbox.xilinx.com/docsan/xilinx82/books/docs/xst/xst.pdf

    -Jason


    Account1 wrote:
    > Hi,
    >
    > The last_value attribute is synthesizable?
    >
    > Could you suggest a link about the synthesizable subset of vhdl?
    >
    > Thanks
    > Attila
    Jason Agron, Dec 26, 2006
    #4
  5. Account1

    Jim Lewis Guest

    Short answer:
    No.

    Long answer:
    IEEE 1076.6-2004 is the current VHDL RTL synthesis standard.
    Unfortunately many vendors have not implemented it yet.
    Usually this is a function of their users asking them to.
    So start asking.

    'last_value is not supported in user code. However, it is
    supported in the functions ieee.std_logic_1164.rising_edge
    and ieee.std_logic_1164.falling_edge.

    There may be vendors who do support it in user code,
    however, that does not mean it will be portable between
    vendors. In fact, historically speaking, Mentor's Autologic
    synthesis tool either supported or required 'last_value.

    WRT 1076.6, there is much work that could be done on attributes.
    I think the best way to get this done is to express interest to
    your vendors that this needs to be done and then form a working
    group under DASC (www.dasc.org). I have some experience with
    this and if there is interest, I could help out with the process
    things.

    What did you want to use 'last_value for?

    Cheers,
    Jim

    P.S.
    There is also 1076.6-1999 which many vendors have implemented -
    primarily since the standard was written so that most vendors
    would be compliant - it was intended to give model writers
    a standard to which they could claim compliance.


    > Hi,
    >
    > The last_value attribute is synthesizable?
    >
    > Could you suggest a link about the synthesizable subset of vhdl?
    >
    > Thanks
    > Attila
    >
    >
    Jim Lewis, Dec 26, 2006
    #5
  6. Account1

    Account1 Guest

    I'd like to use to test rising/falling edge of a signal.
    I think it should be synthesizable because std_logic_1164.rising_edge() uses
    this attribute. I assume when I can use std_logic_1164.rising_edge() I can
    use "last_value" also

    Im not familiar with synthesis (now), I just want write a package which
    items are synthesizable also. I prefer using attributes instead of using
    functions from "std_logic_1164".

    Thanks
    Attila




    "Jim Lewis" <> wrote in message
    news:...
    > Short answer:
    > No.
    >
    > Long answer:
    > IEEE 1076.6-2004 is the current VHDL RTL synthesis standard.
    > Unfortunately many vendors have not implemented it yet.
    > Usually this is a function of their users asking them to.
    > So start asking.
    >
    > 'last_value is not supported in user code. However, it is
    > supported in the functions ieee.std_logic_1164.rising_edge
    > and ieee.std_logic_1164.falling_edge.
    >
    > There may be vendors who do support it in user code,
    > however, that does not mean it will be portable between
    > vendors. In fact, historically speaking, Mentor's Autologic
    > synthesis tool either supported or required 'last_value.
    >
    > WRT 1076.6, there is much work that could be done on attributes.
    > I think the best way to get this done is to express interest to
    > your vendors that this needs to be done and then form a working
    > group under DASC (www.dasc.org). I have some experience with
    > this and if there is interest, I could help out with the process
    > things.
    >
    > What did you want to use 'last_value for?
    >
    > Cheers,
    > Jim
    >
    > P.S.
    > There is also 1076.6-1999 which many vendors have implemented -
    > primarily since the standard was written so that most vendors
    > would be compliant - it was intended to give model writers
    > a standard to which they could claim compliance.
    >
    >
    >> Hi,
    >>
    >> The last_value attribute is synthesizable?
    >>
    >> Could you suggest a link about the synthesizable subset of vhdl?
    >>
    >> Thanks
    >> Attila
    >>
    >>

    >
    Account1, Dec 27, 2006
    #6
  7. Account1

    Jim Lewis Guest

    'event is synthesizable. 'last_value is not necessarily
    portable in synthesis (if it is supported at all).
    For edge detection of a clock for synthesis in user code
    with an "if" statement, I recommend using either rising_edge
    or if you must roll your own then: clk = '1' and clk'event.

    'last_value allows one to be "for-sure for-sure", however,
    for clocks this should not be necessary. Clocks are sacred
    and if they go to 'X' after they start up, something is very
    wrong and if this is a possibility, having one centralized
    assertion to kill the simulation would be sufficient and
    more efficient than having each register clock edge check and
    see if it is a valid edge. For example:

    Clk_watcher: process
    begin
    wait until is_x(Clk) ;
    if now > CLK_START_UP_TIME then
    report "clock is X" severity failure ;
    end if ;
    end process ;

    Note, I would only do this if there was something in the clock
    circuitry that gave it the possibility of going to X.


    > I'd like to use to test rising/falling edge of a signal.
    > I think it should be synthesizable because std_logic_1164.rising_edge() uses
    > this attribute. I assume when I can use std_logic_1164.rising_edge() I can
    > use "last_value" also


    False assumption.
    There is lots in the standard packages that is not synthesized,
    but instead, simply known. Some of this is accomplished by
    using vendor specific attributes.


    > Im not familiar with synthesis (now), I just want write a package which
    > items are synthesizable also. I prefer using attributes instead of using
    > functions from "std_logic_1164".

    Start simple. There is no reason to write a package early on.
    Learn the basics of synthesizable code first.

    Cheers,
    Jim
    Jim Lewis, Dec 28, 2006
    #7
  8. Account1

    Rob Dekker Guest

    "Account1" <> wrote in message news:7f9fd$4591bf23$5665c095$...
    > I'd like to use to test rising/falling edge of a signal.
    > I think it should be synthesizable because std_logic_1164.rising_edge() uses this attribute. I assume when I can use
    > std_logic_1164.rising_edge() I can use "last_value" also


    There are at least a good number of synthesis (and other RTL) tools that will allow 'last_value in an event expression.
    In an event expression, a 'last_value on the tested event signal IS synthesizable and will essentiall synthesize into an inverter.

    So, if you write your own rising_edge/falling_edge functions (I would not know why you want to do that, but any way), then most
    tools should be able to synthesize these from your code (without the need for a pragma or so).

    >
    > Im not familiar with synthesis (now), I just want write a package which items are synthesizable also. I prefer using attributes
    > instead of using functions from "std_logic_1164".


    If you prefer attributes, then do NOT write a package with functions.

    Simply write the clk'event and clk='1' style expressions where you need them.

    If you prefer functions, then use the 1164 functions.

    Either way, there should not be a need to write your own edge-detection functions.

    Rob
    Rob Dekker, Dec 29, 2006
    #8
  9. Rob Dekker schrieb:

    > "Account1" <> wrote in message news:7f9fd$4591bf23$5665c095$...
    > > I'd like to use to test rising/falling edge of a signal.
    > > I think it should be synthesizable because std_logic_1164.rising_edge() uses this attribute. I assume when I can use
    > > std_logic_1164.rising_edge() I can use "last_value" also

    >
    > There are at least a good number of synthesis (and other RTL) tools that will allow 'last_value in an event expression.
    > In an event expression, a 'last_value on the tested event signal IS synthesizable and will essentiall synthesize into an inverter.


    Which is _not_ the logic I would expect in most case using
    'last_value.

    The OP likes to detect all edges on a signal. I guess he likes to have
    synchronous detection of a edge on an asynchronous signal which won't
    be easy synthesisable with the 'last_value.
    Of course the synthesis tool could use a shift-latch which is opend at
    each edge storing the last value of an asynchronous signal but this
    would be error-prone due to race conditions.

    BTW This task is easy done with shift register and an xor.

    bye Thomas
    Thomas Stanka, Dec 29, 2006
    #9
  10. Account1

    KJ Guest

    "Account1" <> wrote in message
    news:7f9fd$4591bf23$5665c095$...
    > I'd like to use to test rising/falling edge of a signal.

    Test for what? It's going to be hard to beat "if rising_edge(signal)
    then..." or "if falling_edge(signal) then..." for clarity of purpose so in
    what way are you helping yourself with your own homegrown 'test'?

    > I think it should be synthesizable because std_logic_1164.rising_edge()
    > uses this attribute. I assume when I can use std_logic_1164.rising_edge()
    > I can use "last_value" also

    As Mike pointed out in his original post, 'try it'

    >
    > Im not familiar with synthesis (now), I just want write a package which
    > items are synthesizable also. I prefer using attributes instead of using
    > functions from "std_logic_1164".

    Why? Is there some problem with using a tested an accepted standard
    package?

    KJ
    KJ, Dec 29, 2006
    #10
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