regarding conversion of form std_logic_vector to std_logic

[ekavirsrikanth]

Hi all,

I am usign Xilinx core gen FIFO (synchronous) where i am using the
data width of 1bit (serial data) but i need the depth of 2pwr 15 for
my application. in core gen one bit data width is specified as
std_logic_ vector (0 downto 0). but i wanted it to be std_logic as my
other modules depend on the std_logic. if i am assigning the
std_logic_ vector directly to std_logic its throwing error in
simulation..... i cannot chnage the entire logic form std_logic to
std_lgic_vector as many sub modules are depend on this .is there any
way that i can change the std_logic_ vector (0 downto 0) to std_logic
by type conversion or any technique.

regards
srikanth

 

[Jonathan Bromley]

is there any
way that i can change the std_logic_ vector (0 downto 0) to std_logic
by type conversion or any technique.

If you have a module with a 1-bit std_logic_vector port, you can
easily connect a std_logic to the only element of that port:

signal S : std_logic;
...
some_instance: some_coregen_component port map (
.... ,
troublesome_vector_port(0) => S,
.... );

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[ekavirsrikanth]

If you have a module with a 1-bit std_logic_vector port, you can
easily connect a std_logic to the only element of that port:

signal S : std_logic;
...
some_instance: some_coregen_component port map (
.... ,
troublesome_vector_port(0) => S,
.... );

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

hi jonathan ... thanks for your reply....
but i have the coregen module as i am instantiating this module in my
top module .... but in coregen module i have it assigned as
std_logic_vector(0 downto 0) but in my top module it is declared as
std_logic.
while intializing as signal in my architcure part i have to make my
top module signals also as std_logic_vector since i need to assign my
top module signal with the coregen signal.......
there it is throwing the error....

error msg:
type error in varible data_in . needed type std_logic_vector.


regards
srik

 

[Jonathan Bromley]

hi jonathan ... thanks for your reply....
but i have the coregen module as i am instantiating this module in my
top module .... but in coregen module i have it assigned as
std_logic_vector(0 downto 0) but in my top module it is declared as
std_logic.

Yes: that is exactly what I'm saying. My code fragment shows
how you can instantiate your coregen component in your own
top module, and connect a std_logic signal in your module
to a std_logic_vector port on the coregen component.

while intializing as signal in my architcure part i have to make my
top module signals also as std_logic_vector

No you don't. See above.

since i need to assign my
top module signal with the coregen signal.......

No. You *connect* your top module signal to a port on
the coregen module, in the way I showed you.
Port connection is *not* an assignment.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[ekavirsrikanth]

Yes: that is exactly what I'm saying. My code fragment shows
how you can instantiate your coregen component in your own
top module, and connect a std_logic signal in your module
to a std_logic_vector port on the coregen component.


No you don't. See above.


No. You *connect* your top module signal to a port on
the coregen module, in the way I showed you.
Port connection is *not* an assignment.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thank you... jonathan ,........ i got it ..... thank you .....


regard
srik