Timing details during synthesis in Xilinx ISE

Discussion in 'VHDL' started by Thunder, Jun 28, 2007.

  1. Thunder

    Thunder Guest

    My program uses one clk (as one of the ports) and every process is
    executed only at the rising edge of the clk. Even then, the synthesis
    report contains no clock information or timing summary. It says "No
    clock signals found in this design"
    The timing summary is given as
    Minimum period: No path found
    Minimum input arrival time before clock: No path found
    Maximum output required time after clock: No path found
    Maximum combinational path delay: No path found

    The device utilization summary is also not complete.

    I will be grateful if you could help me in getting the timing details
    along with the device utilization summary.
     
    Thunder, Jun 28, 2007
    #1
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  2. Thunder

    KJ Guest

    "Thunder" <> wrote in message
    news:...
    > My program uses one clk (as one of the ports) and every process is
    > executed only at the rising edge of the clk. Even then, the synthesis
    > report contains no clock information or timing summary. It says "No
    > clock signals found in this design"
    > The timing summary is given as
    > Minimum period: No path found
    > Minimum input arrival time before clock: No path found
    > Maximum output required time after clock: No path found
    > Maximum combinational path delay: No path found
    >
    > The device utilization summary is also not complete.
    >
    > I will be grateful if you could help me in getting the timing details
    > along with the device utilization summary.
    >

    What is most likely happening either:
    1. No output of the top level design depends on the code that you've written
    so it gets optomized away.
    2. All of the inputs to a lower level block are either open or static (i.e.
    always '1', '0', 'X') possibly because they have not been connected. In
    that situation, the output of the 'clocked' processes can usually be fully
    pre-computed and will also be static again resulting in the logic getting
    optomized away .

    In either case (or any combo of the two) if all registers happen to get
    optomized away there will be no clocked timing paths to analyze which will
    result in the messages that you're seeing about not finding a timing path to
    analyze.

    To fix it, start up the simulator, applying stimulus to the input pins of
    the top level and see if all of the outputs are doing what you want them to
    be doing. What you'll find is that they are not working properly and the
    outputs will likely be static (always, '1', '0', 'X', etc. but not
    changing). Once you get that going you'll find that the logic won't be
    getting optomized away and that the timing analyzer will find timing paths
    to analyze.

    Messages about sections where device utilization is way below what it should
    be (or even 0% utilization) are useful tools to help pinpoint areas of the
    design where you've not connected something up right or are feeding in
    static signals.

    KJ
     
    KJ, Jun 29, 2007
    #2
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  3. Thunder

    KJ Guest

    "KJ" <> wrote in message
    news:5zYgi.4749$...

    > 2. All of the inputs to a lower level block are either open or static
    > (i.e. always '1', '0', 'X') possibly because they have not been connected.
    > In that situation, the output of the 'clocked' processes can usually be
    > fully pre-computed and will also be static again resulting in the logic
    > getting optomized away .


    On item #2 I meant to say 'At least one of the inputs...', not 'All of the
    inputs..'. A single unconnected input can cause an entire block to be
    optomized away. A simple example would be if every input is connected
    except for the clock

    KJ
     
    KJ, Jun 29, 2007
    #3
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