sunil said:
Hi,
I want to generate VCD for my design. Can anybody tell me how to
Using ModelSim do file commands :-
vcd file page_test000_tb.vcd # Creates a standard VCD file
vcd add -ports /test000_tb/u0/* # This only adds the names signals.
# For bi-directionals you may need to
# store the control signals.
ModelSim can create extended VCD files. If you want to create one of
these then the syntax is similar to above. Chapter 13 gives a reasonable
explanation of how to create VCD files.
Here is a *rough* website covering VCD files. It was written from a
verilog perspective. The techniques and checks shouldn't be much
different for VHDL.
http://www.plymouth2.demon.co.uk/vcd_pages/vcdtoc.htm
Constructive criticism will be appreciated.
What are you trying to do? For viewing waveforms the above information
is OK. If you are going to extract test vectors then you need to check
that the waveforms are suitable for the tester.
If anyone knowledge of the VHDL equivalents of the verilog system tasks
dumpfile and dumpvars then I would be interested.
generate for VHDl design. After loading the design, which commandas i
have to execute. I am not using any test bench, i am giving values by
forcing.
It'll be easier to write a testbench surely.