VCD file generation

Discussion in 'VHDL' started by sunil, Apr 23, 2004.

  1. sunil

    sunil Guest

    Hi,
    I want to generate VCD for my design. Can anybody tell me how to
    generate for VHDl design. After loading the design, which commandas i
    have to execute. I am not using any test bench, i am giving values by
    forcing.
    thanking you all.
     
    sunil, Apr 23, 2004
    #1
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  2. Sunil,
    Depends on your simulator, as VCD is not defined in VHDL LRM,
    rather it is part of Verilog LRM. I know that NCSIm & Modelsim
    supports VCD dumping for VHDL too. In NCSIm you could do:

    database -vcd -open my_dump -default
    probe -create -vcd tb_top -depth all

    Check your simulator's documentation for more.

    HTH,
    Ajeetha,
    http://www.noveldv.com
    Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
    Edition.

    (sunil) wrote in message news:<>...
    > Hi,
    > I want to generate VCD for my design. Can anybody tell me how to
    > generate for VHDl design. After loading the design, which commandas i
    > have to execute. I am not using any test bench, i am giving values by
    > forcing.
    > thanking you all.
     
    Ajeetha Kumari, Apr 23, 2004
    #2
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  3. In article <>, sunil
    <> writes
    >Hi,
    > I want to generate VCD for my design. Can anybody tell me how to


    Using ModelSim do file commands :-

    vcd file page_test000_tb.vcd # Creates a standard VCD file
    vcd add -ports /test000_tb/u0/* # This only adds the names signals.
    # For bi-directionals you may need to
    # store the control signals.

    ModelSim can create extended VCD files. If you want to create one of
    these then the syntax is similar to above. Chapter 13 gives a reasonable
    explanation of how to create VCD files.

    Here is a *rough* website covering VCD files. It was written from a
    verilog perspective. The techniques and checks shouldn't be much
    different for VHDL.
    http://www.plymouth2.demon.co.uk/vcd_pages/vcdtoc.htm
    Constructive criticism will be appreciated.

    What are you trying to do? For viewing waveforms the above information
    is OK. If you are going to extract test vectors then you need to check
    that the waveforms are suitable for the tester.

    If anyone knowledge of the VHDL equivalents of the verilog system tasks
    dumpfile and dumpvars then I would be interested.

    >generate for VHDl design. After loading the design, which commandas i
    >have to execute. I am not using any test bench, i am giving values by
    >forcing.


    It'll be easier to write a testbench surely.

    > thanking you all.


    --
    Andy Botterill
     
    Andy Botterill, Apr 23, 2004
    #3
  4. sunil

    sunil Guest

    Hi,
    thanks for u r replies. I required VCd file for power calculation
    in FPGA. I used commnads vcd file sun.vcd
    vcd dumpports -file sun.vcd /totalunit/*.

    It is loading signals. But accorind to format it is not coming. I want
    to load all the switching rates of all signals in my design. It is not
    loading all signals.
     
    sunil, Apr 24, 2004
    #4
  5. In article <>, sunil
    <> writes
    >Hi,
    > thanks for u r replies. I required VCd file for power calculation
    >in FPGA. I used commnads vcd file sun.vcd
    > vcd dumpports -file sun.vcd /totalunit/*.
    >
    >It is loading signals. But accorind to format it is not coming. I want


    If you add a -r the command recursively travels the whole of the design.

    vcd add -r /totalunit/* -file sun.vcd

    >to load all the switching rates of all signals in my design. It is not
    >loading all signals.


    If the design is of any size the resultant extended VCD file will be
    huge.
    --
    Andy Botterill
     
    Andy Botterill, Apr 24, 2004
    #5
  6. sunil

    sunil Guest

    Hi,
    Thanks for u r help. That commnad is working,. I ahve one doubt.
    Whether we have run the program for the real values which we are going
    to use. And How much time it is required to get propoer acitivity
    rates.
    Once again thanks.
     
    sunil, Apr 26, 2004
    #6
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