Viewing internal signals with ModelSim

Discussion in 'VHDL' started by Joseph, Mar 22, 2008.

  1. Joseph

    Joseph Guest

    Hi all,

    I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
    only displays the input/output signals of the simulated top entity.

    Is there a way of viewing the internal signals declared in the
    architecture of the entity without adding them to the port outputs of
    the simulated top entity?

    Thanks very much

    Regards

    Joseph
     
    Joseph, Mar 22, 2008
    #1
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  2. Joseph

    HT-Lab Guest

    "Joseph" <> wrote in message
    news:...
    > Hi all,
    >
    > I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
    > only displays the input/output signals of the simulated top entity.
    >
    > Is there a way of viewing the internal signals declared in the
    > architecture of the entity without adding them to the port outputs of
    > the simulated top entity?
    >
    > Thanks very much
    >
    > Regards
    >
    > Joseph


    Modelsim will optimise your design by default and hence you might loose some
    internal signals, try "log -r *" before running your simulation.

    Hans
    www.ht-lab.com
     
    HT-Lab, Mar 22, 2008
    #2
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  3. Joseph

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
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    Denmark
    Try the ISE simulator - it allows you to watch in internal signals by drag and drop.

    If you then switch to the modelsim with a saved simulation, will the Modelsim give you the internal signals as well (strange ) ;)
     
    jeppe, Mar 22, 2008
    #3
  4. Joseph wrote:
    > Hi all,
    >
    > I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
    > only displays the input/output signals of the simulated top entity.
    >
    > Is there a way of viewing the internal signals declared in the
    > architecture of the entity without adding them to the port outputs of
    > the simulated top entity?
    >

    Sorry if this is obvious, but you have tried descending the hierarchy in
    the "Workspace" window? Signals at the current level are listed in
    "Objects", & you can add them to the display.
     
    David R Brooks, Mar 22, 2008
    #4
  5. Joseph wrote:
    > Hi all,
    >
    > I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim
    > only displays the input/output signals of the simulated top entity.
    >
    > Is there a way of viewing the internal signals declared in the
    > architecture of the entity without adding them to the port outputs of
    > the simulated top entity?
    >
    > Thanks very much
    >
    > Regards
    >
    > Joseph


    I don't know if this will help you, but I've noticed that the new
    version of Modelsim optimizes away internal signals by default. I have
    to use a new argument in vsim:

    vsim -voptargs="+acc" test

    -Kevin
     
    Kevin Neilson, Mar 27, 2008
    #5
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