Viterbi Decoder

Discussion in 'VHDL' started by vex_helix, Jan 7, 2008.

  1. vex_helix

    vex_helix

    Joined:
    Oct 14, 2007
    Messages:
    4
    I am designing r=1/2 k=7 decoder in verilog but don't want to start from scratch. Can someone share decoder implementation for r=1/2 and k=3, etc. which I can use as a basis to develop my code?

    Thanks
    vex_helix, Jan 7, 2008
    #1
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