Altera Quartus II VHDL code compilation process

Discussion in 'VHDL' started by ssylee, Oct 26, 2008.

  1. ssylee

    ssylee Guest

    When a particular VHDL project is compiled in Altera Quartus II, is
    the code converted to digital logic and mapped the gates using look-up
    tables?
     
    ssylee, Oct 26, 2008
    #1
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  2. Synthesis converts well-formed code into a netlist
    of gates (LUTs or MUXes) and flops that simulates the
    same as the code.

    For example, this code:
    http://mysite.verizon.net/miketreseler/count_enable.vhd
    becomes a logical netlist like this,
    http://mysite.verizon.net/miketreseler/count_enable.pdf
    and then a primitive netlist like this:
    http://mysite.verizon.net/miketreseler/count_enable_map.pdf

    -- Mike Treseler
     
    Mike Treseler, Oct 26, 2008
    #2
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