ASIC gate count estimation

[nmatringe]

Hello
I am working on an ASIC specification and I would like to estimate the
digital part's size. The goal is to choose between hard coded logic or
CPU core.
I have analyzed the code and found the basic logic functions (FFs,
AND, OR etc) but can not reduce this to "simple" logic gates (I think
the traditional unit is the 2-input NAND gate)
Anyone got a link or something with the gate equivalent of standard
logic functions ?

Thanks
Nicolas

 

[want.a.friendlier.world]

I would say the best way is to synthesize your code and map it to a
standard cell library.

Simply trying to decompose everything to NAND gates may not be what
you want right now unless you're considering full-custom ASICs, but I
think we'd need more information about what you're trying to do.

 

[mcdjnaja]

I think too you must explain more...

If you are only looking for a coarse assessment of the size to compare, and you have all logic functions in basic logic, you can do a calculus.
Normally, the base is 1 one for an inverter. So you can have a calculus with the number of inverters, the number of and-2 gate (which is an inverter*coefficient), and so on and obtain an area in inverters or and-2 gate and so on.
But for this, you must have a predifined library of gates with values of area of each gate.

 

[Nicolas Matringe]

(e-mail address removed) a écrit :

I would say the best way is to synthesize your code and map it to a
standard cell library.

Simply trying to decompose everything to NAND gates may not be what
you want right now unless you're considering full-custom ASICs, but I
think we'd need more information about what you're trying to do.

I am trying to roughly estimate the size of the digital part of an ASIC
we are planning.
We don't have any synthesis tool, the ASIC will be developped by a
subcontractor (which we haven't chosen yet)

Nicolas

 

[diogratia]

(e-mail address removed) a écrit :



I am trying to roughly estimate the size of the digital part of an ASIC
we are planning.
We don't have any synthesis tool, the ASIC will be developped by a
subcontractor (which we haven't chosen yet)

Gate count estimation using NAND gate sites is typically useful to
find an estimate of the size of the target device needed to implement
a design.

For purposes of generating a NAND gate equivalent estimate for a
design you would need access to a cell library that provides primitive
to NAND gate mappings. You would also need some basic awareness of
requirements for fanout, as a primitive would come in various drive
strengths. Because you are dealing with what is considered the most
primitive element of a design, a NAND gate, almost any cell library
will do for purposes of estimation, as long as fanout rules are
generally compatible.

For instance, the NEC CMOS-8L 0.5 um cell library manual found here:
http://www.eu.necel.com/doclist/index.html
http://www.eu.necel.com/_pdf/A12213XJ5V1UM00.PDF (cell library
manual)

lists on Page 6-58, a 2 input NAND gate as 1 'cell', without
additional fan out drive or inverters, telling us that a cell is a
NAND gate. All the primitives are sized in cells.

Because ASIC designs are typically in the hundreds of thousands of
gates it is useful to use a silicon synthesizer to report gate
equivalents, or have a silicon vendor make the estimate from an RTL
netlist. You can 'audit' your design and use a spreadsheet to
generate the NAND gate counts. Making rough estimates generally
involves learning a feel for fudge factors, and leaving headroom in a
design based on the need for fanout and trace length. A simple
estimate can be used to bracket two or three devices in increasing
sizes for cost estimate purposes.

A lot of vendors require a customer relationship before disclosing
cell library manuals, or don't provide them at all. Historically the
manuals contained information of value to a competitor. Vendors can
also require a tool chain that can be used without manuals.

Contacting a potential vendor help in pricing is always in order. The
economics of what you're trying to do become clear quite quickly.
They would also provide leads on finding contractors.

 

[Jim Lewis]

Nicolas

(e-mail address removed) a écrit :


I am trying to roughly estimate the size of the digital part of an ASIC
we are planning.
We don't have any synthesis tool, the ASIC will be developped by a
subcontractor (which we haven't chosen yet)

Off topic, but notable, there are a couple of ASIC vendors
who will translate your FPGA to ASIC for you. So if you have
FPGA tools, you may be able to spin it into an ASIC in an easy
fashion. One thing to watch in this fashion is that ASICs do not
have built-in power-on reset and any FPGA logic that used this
would need to be reset with the reset input.

One vendor who does this is AMI. See
http://www.amis.com/conversion/

There are probably others also.

Cheers,
Jim

 

[mk]

Hello
I am working on an ASIC specification and I would like to estimate the
digital part's size. The goal is to choose between hard coded logic or
CPU core.
I have analyzed the code and found the basic logic functions (FFs,
AND, OR etc) but can not reduce this to "simple" logic gates (I think
the traditional unit is the 2-input NAND gate)
Anyone got a link or something with the gate equivalent of standard
logic functions ?

If you have no other avenue of getting your logic synthesized (I can
do it for you if you're willing to send the rtl) you can use the
following VERY rough way to estimate. For every flop count 6 gates,
for every logic function with N inputs count N/2 gates, for every bit
of memory count 3 gates and add all up. You should get a 1/2x->2x
estimate of the gate count.
Hth.

 

[nmatringe]

Off topic, but notable, there are a couple of ASIC vendors
who will translate your FPGA to ASIC for you. So if you have
FPGA tools, you may be able to spin it into an ASIC in an easy
fashion. One thing to watch in this fashion is that ASICs do not
have built-in power-on reset and any FPGA logic that used this
would need to be reset with the reset input.

One vendor who does this is AMI. Seehttp://www.amis.com/conversion/

Hello Jim
I know AMIS, we met them a few weeks ago.
The problem here is that our ASIC will be mixed-signal (and AMIS has
nice features to offer in this area too)
Thanks anyway

Nicolas

 

[nmatringe]

If you have no other avenue of getting your logic synthesized (I can
do it for you if you're willing to send the rtl) you can use the
following VERY rough way to estimate. For every flop count 6 gates,
for every logic function with N inputs count N/2 gates, for every bit
of memory count 3 gates and add all up. You should get a 1/2x->2x
estimate of the gate count.
Hth.

Thanks a lot, that's exactly the kind of rule of thumb I was looking
for.

Nicolas

 

[moogyd]

If you have no other avenue of getting your logic synthesized (I can
do it for you if you're willing to send the rtl) you can use the
following VERY rough way to estimate. For every flop count 6 gates,
for every logic function with N inputs count N/2 gates, for every bit
of memory count 3 gates and add all up. You should get a 1/2x->2x
estimate of the gate count.
Hth.

Hi,

I use an even rougher rule of thumb.

Gate Count = Number FF's * 20

To get an idea of gate counts, try looking at opencores website, I
think that they sometimes have gatecounts with the IP's which may give
you some idea.

Steven

Steven

This

 

[toanbkfet]

hello you have document speak of count gate nand 2 ??

if you have ?? can you spent document that??

 

[Nikolaos Kavvadias]

This is a 6-year old thread, no much point in adding new posts.

Τη ΤετάÏτη, 14 ΜαÎου 2014 6:59:22 μ.μ. UTC+3, ο χÏήστης (e-mail address removed) έγÏαψε: