assignment constraint check time

Discussion in 'VHDL' started by Valentin Tihhomirov, Jan 21, 2013.

  1. I read (ashenden) that "The operations produce values of the base type
    rather than the sub-type. However, the assignment operation will not
    assign a value to a variable of a subtype if the value does not meet the
    constraint".

    I do not understand when this check is performed. One one hand, VHDL
    must do this statically, to stay the statically typed lang. On the other
    hand, dynamically, because evaluation occurs in simulation and you
    cannot check the result before it is produced. I see no way you can
    check the range before simulation starts but after it finishes.
     
    Valentin Tihhomirov, Jan 21, 2013
    #1
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  2. Valentin Tihhomirov

    KJ Guest


    Given this definition...
    signal xyz: integer range 0 to 2;

    The following will be caught by the compiler before the simulation starts...
    xyz <= 3; -- Will be caught up front when first compiled

    The following will be caught by the simulator at run time
    process
    begin
    xyz <= 0;
    for i in 1 to 10 loop
    xyz <= xyz + 1; -- Will be caught at run time when xyz is currently three
    end loop;
    end process;

    What are you confused about?

    Kevin
     
    KJ, Jan 21, 2013
    #2
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  3. I can easily repeat my question: how do you call a language strongly
    typed if it admits assigning values outside the range?

    I start to understand. Range check is a subtype feature. Being strongly
    typed is not the same as strongly subtyped. VHDL may postpone the
    subtype range check until after execution and still remain a strongly
    typed because only subtype range may fail at runtime but not type range!
    If this is right, then my another question, what is the base type,
    starts sounding more important. Can you answer it?
     
    Valentin Tihhomirov, Jan 21, 2013
    #3
  4. I can easily repeat my question: how do you call a language strongly
    typed if it admits assigning values outside the range?

    I start to understand. Range check is a subtype feature. Being strongly
    typed is not the same as strongly subtyped. VHDL may postpone the
    subtype range check until after execution and still remain a strongly
    typed because only subtype range may fail at runtime but not type range!
    If this is right, then my another question, what is the base type,
    starts sounding more important. Can you answer it?
     
    Valentin Tihhomirov, Jan 21, 2013
    #4
  5. Valentin Tihhomirov

    valtih1978 Guest

    You say that there is no need to make any checks at compile time since
    strongly typed runtime prevents us from making an incompatible
    assignment. This is not what I call a "strongly typed" system. By
    strongly typed I mean not detection but prevention of incompatible
    assignments. Am I wrong?

    I recall those annoying "outside the range" simulator-firing errors.
    Surprisingly, I have never mentioned anything like this in another
    strongly typed system - Java. The fact that I can assign a short to into
    in java means that short is a subtype of int. Yet, when I assign an
    "int"-producing expr to a "short" value, compiler asks me to infer an
    explicit cast that prevents errors happening at runtime. Might be this
    is because Java follows the following rule that I see in Wikipedia:

    Strongly typing means

    *Omission of implicit type conversion*, that is, conversions that are
    inserted by the compiler on the programmer's behalf. For these authors,
    a programming language is strongly typed if type conversions are allowed
    only when an explicit notation, often called a cast, is used to indicate
    the desire of converting one type to another."

    One of the rules says that "Static typing is often confused with Strong
    Typing". Dear, it seems to be my case :)
     
    valtih1978, Jan 21, 2013
    #5
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