Automatic Schematic Generation (System Graph) and Viewer

[Alfonso Acosta]

Hi all,

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe: http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Does any one know about a specific, open file format for schematics?
My best options so far are GXL (http://www.gupro.de/GXL/) and GraphML
(http://graphml.graphdrawing.org/) but I coudn't find any free viewer
with automatic routing support.

Any help would be appreciated. Thanks in advance,

Alfonso Acosta

 

[Mike Treseler]

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe: http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

I expect that not all 5 newsgroups would be interested
even if it were finished.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

This has been done.
Most synthesis tools have an RTL viewer which
generates schematics and state graphs from a netlist.
Google a bit.

Does any one know about a specific, open file format for schematics?

Common netlist formats are edif, verilog and vhdl.

My best options so far are GXL (http://www.gupro.de/GXL/) and GraphML
(http://graphml.graphdrawing.org/) but I coudn't find any free viewer
with automatic routing support.

Low cost backend tools are device specific.
Few are free.

-- Mike Treseler

 

[Clunixchit]

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Try the Alliance VLSI CAD, it is free and open source.

http://www-asim.lip6.fr/recherche/alliance/

One of its tools, boog can take a HDL model and generates a schematic
which can be read with its xsch schematic viewer.

PS: try it under a redhat or fedora based distribution or its clones.
On a debian based distro, I had problems in installing alliance to be
used with other commercial products.

Chitlesh

 

[krw]

Hi all,

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe: http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Synplify Pro does (with HDL Analyst). It also generates bubble
charts (something you might think about doing also).

<snip>

 

[Shannon]

Synplify Pro does (with HDL Analyst). It also generates bubble
charts (something you might think about doing also).

<snip>

Quartus II also has an RTL view and state-machine bubble viewer.
ModelSim does as well. In fact, do any of the major tools NOT have a
schematic viewer?

Shannon