I have a bug in a test fixture that is FPGA based. I had thought it was\nin the software which controls it, but after many hours of chasing it\naround I've concluded it must be in the FPGA code.\n\nI didn't think it was in the VHDL because it had been simulated well and\nthe nature of the bug is an occasional dropped character on the receive\nside. Who can't design a UART? Well, it could be in the handshake with\nthe state machine, but still...\n\nSo I finally got around to adding some debug signals which I would\nmonitor on an analyzer and guess what, the bug is gone! I *hate* when\nthat happens. I can change the code so the debug signals only appear\nwhen a control register is set to enable them, but still, I don't like\nthis. I want to know what is causing this DURN THING!\n\nAnyone see this happen to them before?\n\nOh yeah, someone in another thread (that I can't find, likely because I\ndon't recall the group I posted it in) suggested I add synchronizing FFs\nto the serial data in. Sure enough I had forgotten to do that. Maybe\nthat was the fix... of course! It wasn't metastability, I bet it was\nfeeding multiple bits of the state machine! Durn, I never make that\nsort of error. Thanks to whoever it was that suggested the obvious that\nI had forgotten.