confusion with ADC/DAC interface implementation

Discussion in 'VHDL' started by alkosd, Apr 23, 2010.

  1. alkosd

    alkosd Guest

    i am confused regarding the ADC/DAC interface implementation on FPGA.
    I have read a code where after serialising the input data of 16 bits
    in 16 clock cycles, the interface logic loops (in vain?) for another
    16 cyles before serialising the next data. can#t understand why? why
    the serialisation of the next data is not done immediately. moreover,
    should the serialisation clock rate be 16 higher than the data stream
    clock rate? Sorry but i could not find a documentation detailing all
    the synchronization mechanism.

    cheers :)
    alkosd, Apr 23, 2010
    1. Advertisements

  2. alkosd

    KJ Guest

    Because things work as they are designed...not as they are intended.

    Do you have a specific question or are you trolling and asking the
    group to fathom why some unlisted code that is implemented in an FPGA
    either keeps reading from an ADC or keeps writing to a DAC or perhaps
    Thought you just said it tried again, as you say "in vain?"...sounds
    immediate to me
    If the ADC shifts out 16 bits of data, then yes it would need to be at
    least 16 times as fast as you'd like to sample the analog data.
    Are you asking the group to find the documentation for you?

    What you need is the datasheet for whatever ADC or DAC that you're
    talking about.

    Try a more informed posting after you've put some though into your
    question and provide some actual details of what you don't understand
    and you'll likely get better responses.

    KJ, Apr 23, 2010
    1. Advertisements

  3. alkosd

    Tricky Guest

    Wow - grouchy this morning. Did someone piss on your cocoa-pops? ;)
    Tricky, Apr 23, 2010
  4. alkosd

    Górski Adam Guest


    Please specify your ADC DAC type.


    Górski Adam, Apr 23, 2010
  5. alkosd

    HT-Lab Guest

    As suggested by others your question is very vague, however, some SPI ADC have
    the option to stream out the LSB first. In order to do this you first need to
    stream out the MSB_first word and then you can read the LSB_first word (this
    makes perfect sense for a successive approximation ADC). Thus in the LSB case
    you need 2 sets of n-bit clock cycles.

    Find the datasheets and (hopefully) all should become clear,

    HT-Lab, Apr 23, 2010
  6. alkosd

    alkosd Guest

    thank you for the advice. I got the datasheet at last! i'll work on
    the details now. thank you again
    alkosd, Apr 23, 2010
  7. alkosd

    JimLewis Guest

    For details of this, look up a UART in a text book.

    Here is a hint in the right direction.
    Assume that data (digital or analog) is transmitted between two
    at a certain rate, but asynchronously ie: no clock in the interface.
    Can the receive clock be the same frequency of the transmit clock?
    Assume there is no way to guarantee any relationship between the
    two clocks. In fact, it is common for them to be slightly
    different in frequency.

    If the sample clock is 16X faster than the transmit, the middle
    of a cycle is found when a start indication is found 8 times.
    Then capturethe data values once every 16 times (because the
    receive clockis 16X faster). With this slight differences in
    can be tolerated - depending how many samples are taken between
    realigning with a start bit.

    Good Luck,
    SynthWorks VHDL
    JimLewis, Apr 27, 2010
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.