A
alkosd
Hi,
i am confused regarding the ADC/DAC interface implementation on FPGA.
I have read a code where after serialising the input data of 16 bits
in 16 clock cycles, the interface logic loops (in vain?) for another
16 cyles before serialising the next data. can#t understand why? why
the serialisation of the next data is not done immediately. moreover,
should the serialisation clock rate be 16 higher than the data stream
clock rate? Sorry but i could not find a documentation detailing all
the synchronization mechanism.
cheers
i am confused regarding the ADC/DAC interface implementation on FPGA.
I have read a code where after serialising the input data of 16 bits
in 16 clock cycles, the interface logic loops (in vain?) for another
16 cyles before serialising the next data. can#t understand why? why
the serialisation of the next data is not done immediately. moreover,
should the serialisation clock rate be 16 higher than the data stream
clock rate? Sorry but i could not find a documentation detailing all
the synchronization mechanism.
cheers