Convert Real number to Std_logic_vector

[Sudhir]

Hi

I Have 2 constant values nu= 3.131764231e-3
and v = 0.993736471

Later on in my VHDL code I have to multiply these with two values
which are std_logic_vectors of 20bits. So I would like to convert
these constants to vectors of 20 bits without losing precision.How
could I do so in VHDL

tried to do conv_std_logic_vector(nu,20); unfortunately it didnt work!

Please if anyone could help me I would be grateful

Thanks

Sudsy

 

[KJ]

Hi

I Have 2 constant values nu= 3.131764231e-3
and v = 0.993736471

Later on in my VHDL code I have to multiply these with two values
which are std_logic_vectors of 20bits. So I would like to convert
these constants to vectors of 20 bits without losing precision.How
could I do so in VHDL

You can't. The real numbers are represented with more than 20 bits of
precision so converting them to 20 std_logic_vectors will result in lost
precision.

tried to do conv_std_logic_vector(nu,20); unfortunately it didnt work!

Because you can't convert a real to a std_logic_vector using this function.

Please if anyone could help me I would be grateful

Convert the std_logic_vectors into real numbers and keep the full precision
of your calculation.

Also since your attempt used the 'conv_std_logic_vector' this implies that
you're using the 'ieee.std_logic_arith' package. This package is not a
standard and really should not be used. Use the ieee.numeric_std package
instead and you'll save yourself some headaches down the road.

Kevin Jennings

 

[David Bishop]

Hi

I Have 2 constant values nu= 3.131764231e-3
and v = 0.993736471

Later on in my VHDL code I have to multiply these with two values
which are std_logic_vectors of 20bits. So I would like to convert
these constants to vectors of 20 bits without losing precision.How
could I do so in VHDL

tried to do conv_std_logic_vector(nu,20); unfortunately it didnt work!

Please if anyone could help me I would be grateful

First off, these are real numbers. Real numbers don't synthesize.
Internally they are represented as 64 bit floating point numbers.

I would recommend using fixed point. Then you can convert the numbers
into something synthesizable.

http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html
For the documentation.

For code to synthesize, look at:
http://www.vhdl.org/fphdl/vhdl.html