# distorted sine wave

Discussion in 'VHDL' started by FPGA, Feb 15, 2008.

1. ### FPGAGuest

I have written a process to generate sine wave. I am getting a
distorted wave and not a pure sine wave. I am not sure if this has
anything to do with the simulator.

two : process
variable phase_temp,result : real;
constant scale : real := 2.0*real(bw);
begin
phase_temp := phase_sin; --phase_sin;
l1 : for i in 1 to samples_sin loop --number_of_samples loop
result := scale*(amp_sin*(sin(frq_sin + phase_temp)));
sine_real <= (amp_sin*(sin(frq_sin + phase_temp)));
sinWave <= toSigned(result,bw);
phase_temp := phase_temp+incr_sin;
wait for 5 ns;
end loop l1;

end process two;

generic value : phase_sin : real := 0.0; samples_sin : integer :=
1000; incr_sin : real := 1.0;
frq_sin : real := 1000.0;

I dont see the frequency of the wave change if the frq_sin is changed.
Same happens when samples_sin is changed. I am not sure what is going

FPGA, Feb 15, 2008

2. ### John_HGuest

Your frq_sin value is actually just a phase offset. There is no time
associated with this constant to feed the sin(). The phase_temp, on
the other hand, is effectively t*incr_sin where t is a cycle count.
To see the frequency change, change the incr_sin value instead.

In what way is your sine distorted?

- John_H

John_H, Feb 15, 2008

3. ### FPGAGuest

How can I pass time parameter to the sineWave? I was able to remove
the distortion by reducing the incr_sin value. Still not clear on the
frequency and time parameter that you are talking about.

FPGA, Feb 15, 2008
4. ### noneGuest

Change incr_sin to .1 and look at the difference in the waveform.
You are stepping through the sine wave in 6 steps so you will not
see what you expect. The wave will look a lot prettier with more
steps.

none, Feb 15, 2008
5. ### Dwayne DilbeckGuest

Time is being implied in your phase assignment. But you are not coding the
frequency generation correctly.

You code mathematiclly is saying the following
y=A*sin(fq+x)
x=x+c
Where fq is frq_sin, and c is incr_sin the sin wave cycle lasts from 0 to
2PI. There is no time or frequency associated with it. Your fq is just
offseting the start point not seting a period. What you want to do is the
following.
x=x+c
y=A*sin(2*PI*fq*x)
now remember that x is being incremented in time. fq is in hz. You need to
inverse fq to get your period time. which yeilds.
x=x+c;
y=A*sin(2*PI*x/tp)
where tp is the cycle length.

Your code should look like so:

for i in 1 to samples_sin loop
result:= scale*(amp_sin*(sin(2.0*PI*frq_sin*phase_temp);
sine_real<=(amp_sin*(sin(2.0*MATH_PI*frq_sin*phase_temp);
sineWave<=toSigned(result,bw)
phase_temp:= phase_temp+incr_sin;
wait for 5 ns; ---Note: This 5ns is not setting the actual frequncy result
with this code
end loop;

--to see a full sine wave cycle set the following:
phase_sin=0.0;
frq_sin=1000; --(1khz)
samples_sin=1000;
incr_sin=0.000001--(1ms/1000 samples)

With this code the "5ns" doesn't do anything constructive. But you could
change the code to make it useful

If you want the time display of the code to match the values that are given
in my comments use "wait for 1us"

Just looking at the time display based on the above code would apear to have
a 200MHZ
sign wave. (1us/5ns)=200, 200*(1 khz)=200Mhz

How can I pass time parameter to the sineWave? I was able to remove
the distortion by reducing the incr_sin value. Still not clear on the
frequency and time parameter that you are talking about.

Dwayne Dilbeck, Feb 15, 2008
6. ### John_HGuest

Phase accumulators are used to mark the prograssion of time. You want
sin(f*T) which is sin(f*n*deltaT) where deltaT is your clock period.
f*n*deltaT is the same as sum from 1 to n of f*deltaT, this last item
being a constant.

That's what you're doing with the incr_sin, isn't it? If you have an
increment of 1/100 of a sinusoidal period, the sum of 100 increments
will be one sinusoidal period bringing you right back to the
beginning.

You *are* doing this for simulation only, aren't you?

- John_H

John_H, Feb 15, 2008
7. ### FPGAGuest

This is for simulation only. Thanks for all your comments. I will make
the suggested changes and let you guys know how it went.

FPGA, Feb 17, 2008