Does the last elseif run or not?

Discussion in 'VHDL' started by fl, Feb 24, 2013.

  1. fl

    fl Guest

    I have the testbench generated by Matlab HDL coder below the dot line.
    Signal "filter_out_rdenb" is connected to a filter CE_OUT component pin (This filter is the DUT of this testbench).

    I am curious about line ld. It has the condition line la:


    then line lb through le will has condition: "filter_out_rdenb='0'". Is this right?

    But it again check
    lc: ELSIF filter_out_rdenb = '1'
    at line lc.

    I think ld will never be run. Does Matlab HDL Coder wrong?
    Or this is intentional to test an abnormal filter CE_OUT condition? I cannot imagine it now. Could you tell me that if that is right?


    checker_1: PROCESS(clk, reset)
    IF reset = '1' THEN
    filter_out_timeout <= 0;
    filter_out_errCnt <= 0;
    filter_out_testFailure <= '0';
    ELSIF clk'event and clk ='1' THEN
    la: IF filter_out_rdenb = '1' THEN
    filter_out_timeout <= 0;
    IF filter_out /= filter_out_expected THEN
    filter_out_errCnt <= filter_out_errCnt + 1;
    filter_out_testFailure <= '1';
    REPORT "Error in filter_out: Expected "
    & to_hex(filter_out_expected)
    & " Actual "
    & to_hex(filter_out)
    IF filter_out_errCnt >= MAX_ERROR_COUNT THEN
    REPORT "Number of errors have exceeded the maximum error"
    SEVERITY Warning;
    END IF;
    END IF;
    lb: ELSIF filter_out_timeout > MAX_TIMEOUT AND filter_out_rdenb = '1' THEN
    filter_out_errCnt <= filter_out_errCnt + 1;
    filter_out_testFailure <= '1';
    REPORT "Timeout: Data was not received after timeout."
    lc: ELSIF filter_out_rdenb = '1' THEN
    ld: filter_out_timeout <= filter_out_timeout + 1 ;
    le: END IF;
    END IF;
    END PROCESS checker_1;
    fl, Feb 24, 2013
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  2. Hello

    Le 24/02/2013 20:39, fl a écrit :
    This makes no sense, every condition tests for filter_out_rdenb = '1'.
    Conditions lb and lc will always be false or overriden by la.

    I've never trusted automatic code generation and this is not going to
    make me change my mind...

    Nicolas Matringe, Feb 24, 2013
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  3. fl

    rickman Guest

    Not only will the section under 1c not run, the condition at 1b will
    never evaluate as true and so that section can never run either. Unless
    there is something I'm missing that would make the structure different
    from the indentation this code is rather bogus. How was the code
    generated? What are the inputs?

    I would report it to MatLab.

    rickman, Feb 24, 2013
  4. fl

    fl Guest

    Thanks both of you. This testbench is for a filter:

    u_hcic: hcic
    PORT MAP (
    clk => clk,
    clk_enable => clk_enable,
    reset => reset,
    filter_in => filter_in,
    filter_out => filter_out,
    ce_out => h_ce_out );

    I have a further question to ask here. I have several years experience of digital circuits design, including EPLD and small implementation on FPGA. For testbench, I assumed it was not a big problem at all in the past. Occasionally I programmed small VHDL code. I used Matlab/Simulink for a medium algorithm project. Recently, I realize that there are some importance on the testbench. I do not find a tutorial or book useful for me on this subject.

    Conceptually, testbench can test suspicious point/component in a big design.. At least there are some techniques to write code on different hierarchy levels etc. Could you tell me any web site, web links on testbench tutorials, typical examples?

    fl, Feb 24, 2013
  5. fl

    Andy Guest

    I highly recommend "Writing Testbenches: Functional Verification of HDL Models", by Janick Bergeron.

    If you plan on writing tesbenches in verilog or VHDL, the first edition (blue cover) is actually better than the second edition (red cover), which has less detail on VHDL/Verilog in favor of other verification languages.

    Janick also has a similar book for SystemVerilog, but I am not familiar with it.

    You might also be interested in Open Source VHDL Verification Methodology ( It is a VHDL library of packages written by Jim Lewis for constrained random pattern generation and coverage modeling.

    Andy, Feb 25, 2013
  6. fl

    Reuven Guest

    I also recommend using the OVL library for verification. Use the VHDL only checkers is you only have a VHDL simulator license.
    Reuven, Feb 27, 2013
  7. fl

    HT-Lab Guest

    Sorry for the people who worked hard on the OVL but I actually wouldn't
    recommend it, at least not to everybody. If you are serious about
    assertions and functional verification than dive straight into PSL or SVA.

    When I tried the latest OVL library I was actually struggling to get a
    simple checker working. Only when I played with the ovl_ctrl_record did
    I managed to get it up and running. The same checker was just a single
    line of PSL (excluding the default clock statement etc).

    Another slight disadvantage is that a large number of VHDL checkers call
    the Verilog version and hence you need a dual language license.

    Get yourself Modelsim DE or the Aldec equivalent and start using PSL,
    you can pick up basic PSL in just a few hours, it is not difficult.

    What would be great if Doulos decided to allocate one of their free 1
    hour training courses to PSL (I know they read this newsgroup :)

    HT-Lab, Feb 28, 2013
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