D
Daku
Could some VHDL guru please help ? I am trying to generate a jittery
clock pulse e.g., clock pulses with pulse width jitter distributed in
an uniform distribution, within pre-defined upper and lower bounds,
e.g., something similar to $dist_uniform in Verilog. Any hints
suggestions would be of immense help.
Thank you.
clock pulse e.g., clock pulses with pulse width jitter distributed in
an uniform distribution, within pre-defined upper and lower bounds,
e.g., something similar to $dist_uniform in Verilog. Any hints
suggestions would be of immense help.
Thank you.