Does VHDL support standard probability distributions

D

Daku

Could some VHDL guru please help ? I am trying to generate a jittery
clock pulse e.g., clock pulses with pulse width jitter distributed in
an uniform distribution, within pre-defined upper and lower bounds,
e.g., something similar to $dist_uniform in Verilog. Any hints
suggestions would be of immense help.
Thank you.
 
M

Martin Thompson

Jonathan Bromley said:
Don't touch the seed variables - just prime them with some
value,

Clearly one of the them should be initialised to '42', but what about
the other one :)

Cheers,
Martin
 

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