- Joined
- Jun 2, 2010
- Messages
- 14
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- 0
In VHDL Mode, what exactly does 'Upper Case Enumeration Values' and 'Upper Case Constants' do?
If it's supposed to turn:
" type state is (idle, transfer, done);
...
case state is
when idle =>"
TO
" type state is (IDLE, TRANSFER, DONE);
...
case state is
when IDLE =>"
AND
"constant test : std_logic_vector(9 downto 0) := (others => '0');"
"constant TEST : std_logic_vector(9 downto 0) := (others => '0');"
then mines not working.. but I don't know that's for sure because I'm not exactly sure what it does or how to get it to work.
Does anyone know how to fix this or get it to work?
If it's supposed to turn:
" type state is (idle, transfer, done);
...
case state is
when idle =>"
TO
" type state is (IDLE, TRANSFER, DONE);
...
case state is
when IDLE =>"
AND
"constant test : std_logic_vector(9 downto 0) := (others => '0');"
"constant TEST : std_logic_vector(9 downto 0) := (others => '0');"
then mines not working.. but I don't know that's for sure because I'm not exactly sure what it does or how to get it to work.
Does anyone know how to fix this or get it to work?