Error: VHDL Use Clause error at quartustest.vhd(6): design library "IEEE" does not contain primary u

[feiyang]

use quartus 5.0
when compile a project, give this messege:
Error: VHDL Use Clause error at quartustest.vhd(6): design library "IEEE"
does not contain primary unit "std_logic_textio"
how can i solve?

 

[Ajeetha]

TEXTIO is intended for simulation alone, not for synthesis, since
Quartus is a synthesizer it doesn't like it. Why do you have that in
your RTL file? Or may be you are passing your tetsbench file to
Quartus?

Regards
Ajeetha, CVC
www.noveldv.com