Execution of a process without an event occurring in its sensitivity list

Discussion in 'VHDL' started by Raja Harsha, Mar 3, 2014.

  1. Raja Harsha

    Raja Harsha Guest

    Hi,

    Is it possible that a process gets executed even when there is no change in the inputs given in the sensitivity list?
    For example,

    Process (x,y,z)
    begin

    if a='1' then
    c<=d+f;
    p=r-q;
    end if;

    end process;

    In the above program, if i change a or d or any other input except x or y or z, does the process get executed?

    I have read in some literature that a process gets executed only once by default and then only when there is a change in signals mentioned in the sensitivity list.
     
    Raja Harsha, Mar 3, 2014
    #1
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  2. Raja Harsha

    KJ Guest

    That is correct.

    Kevin Jennings
     
    KJ, Mar 3, 2014
    #2
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  3. Raja Harsha

    GaborSzakacs Guest

    You should qualify this by saying it's correct for simulation. For
    synthesis the tool will normally assume that there is complete
    coverage in the sensitivity list, and it will generate logic that
    depends on all inputs regardless of whether there is a change on
    x, y, z or not. On the other hand the way the question was worded,
    I assume means we're talking about simulation, because there's
    no concept of a process being executed in the synthesized hardware.
     
    GaborSzakacs, Mar 3, 2014
    #3
  4. Raja Harsha

    GaborSzakacs Guest

    I forgot to add that the synthesis tool will also generate a warning
    when it completes the sensitivity list for you, indicating that your
    hardware implementation may not match the behavioral simulation.
     
    GaborSzakacs, Mar 3, 2014
    #4
  5. Raja Harsha

    Daniel Kho Guest

    You should qualify this by saying it's correct for simulation. For
    Yes, what Gabor said is correct. Synthesis tools usually trigger processes by inferring all inputs instead of looking at the sensitivity list. This isone of the few things that synthesis tools tend to behave differently fromsimulation tools. I still prefer that synthesis tools infer no logic when none of the signals in the sensitivity list changes. Simulation tools follow the standard more strictly than synthesis tools in this respect.
     
    Daniel Kho, Mar 4, 2014
    #5
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